公开(公告)号：US20250048002A1

公开(公告)日：2025-02-06

申请号：US18363469

申请日：2023-08-01

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Hiroaki Ebihara ,  Nobuhiro Yanagisawa ,  Satoshi Sakurai ,  Tomoyasu Tate ,  Naoki Kitazawa ,  Kohei Harada

IPC: H04N25/78 ,  H04N25/709 ,  H04N25/76

Abstract: An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

公开(公告)号：US11483502B1

公开(公告)日：2022-10-25

申请号：US17339692

申请日：2021-06-04

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Wei Deng ,  Tomoyasu Tate ,  Rui Wang

IPC: H04N5/369 ,  H04N5/347 ,  H04N5/351 ,  H04N5/378 ,  H04N5/374 ,  H04N9/04 ,  H01L27/146 ,  H04N5/3745

Abstract: An imaging device includes a pixel array including pixel circuits arranged into rows and columns. Each bitline of a plurality of bitlines is coupled to a respective column of pixel circuits of the pixel array. The plurality of bitlines is grouped into pairs of bitlines. A plurality of binning circuits is coupled to the plurality of bitlines. Each binning circuit is coupled to a respective pair of bitlines and is responsive to a multi-mode select signal. Each binning circuit is configured to output a binned signal responsive to the first and second bitlines of the respective bitline pair in a first mode. Each binning circuit is configured to output a first signal from a first bitline of the respective bitline pair in a second mode. Each binning circuit is configured to output a second signal from the second bitline of the respective bitline pair in a third mode.