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    Integrating ramp circuit with reduced ramp settling time
    5.
    发明授权
    Integrating ramp circuit with reduced ramp settling time 有权

    公开(公告)号：US10826470B2

    公开(公告)日：2020-11-03

    申请号：US16352673

    申请日：2019-03-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Liang Zuo ,  Rui Wang ,  Hiroaki Ebihara ,  Nijun Jiang

    IPC: H03K4/56 ,  H04N5/3745 ,  H03M1/56 ,  H04N5/378 ,  H04N5/369 ,  H03F3/45

    Abstract: A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.

    CMOS image sensor with divided bit lines
    6.
    发明授权
    CMOS image sensor with divided bit lines 有权

    公开(公告)号：US10750111B2

    公开(公告)日：2020-08-18

    申请号：US16222832

    申请日：2018-12-17

    Applicant: OmniVision Technologies, Inc.

    Inventor： Hiroaki Ebihara ,  Rui Wang ,  Zheng Yang ,  Eiichi Funatsu

    IPC: H04N5/378 ,  H01L27/146 ,  H04N5/374

    Abstract: An image sensor includes a pixel array including a plurality of pixels. A bit line coupled to a column of pixels is separated in to a plurality of electrically portions that are coupled to corresponding portions of rows of the pixel array. A first switching circuit of a readout circuit is coupled to the bit line. A first switching circuit is configured to couple a bit line current source to the bit line to provide a DC current coupled to flow through the bit line and through the first switching circuit during a readout operation of a pixel coupled to the bit line. A second switching circuit is configured to couple and ADC to the bit line during the readout operation of the pixel. Substantially none of the DC current provided by the bit line current source flows through the second switching circuit during the readout operation of the pixel.

    SMALL PIXELS HAVING DUAL CONVERSION GAIN PROVIDING HIGH DYNAMIC RANGE
    7.
    发明申请
    SMALL PIXELS HAVING DUAL CONVERSION GAIN PROVIDING HIGH DYNAMIC RANGE 审中-公开

    公开(公告)号：US20190386057A1

    公开(公告)日：2019-12-19

    申请号：US16008434

    申请日：2018-06-14

    Applicant: OmniVision Technologies, Inc.

    Inventor： Rui Wang ,  Zheng Yang ,  Hiroaki Ebihara ,  Tiejun Dai

    IPC: H01L27/146

    Abstract: A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.

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