公开(公告)号：US12284376B2

公开(公告)日：2025-04-22

申请号：US17673039

申请日：2022-02-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/46 ,  H04N19/105 ,  H04N19/169 ,  H04N19/172 ,  H04N19/423 ,  H04N19/44

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry encodes, per temporal sub-layer, one or more hypothetical reference decoder (HRD) parameters into an HRD-related supplemental enhancement information (SEI) message, the one or more HRD parameters being one or more parameters for an HRD, the one or more parameters being related to a decoding unit, the HRD-related SEI message being an SEI message related to the HRD.

公开(公告)号：US12262058B2

公开(公告)日：2025-03-25

申请号：US18231933

申请日：2023-08-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/112 ,  H04N19/119 ,  H04N19/12 ,  H04N19/16 ,  H04N19/17 ,  H04N19/184 ,  H04N19/186 ,  H04N19/30 ,  H04N19/60

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry. In operation, the circuitry: performs a mapping process of Luma Mapping with Chroma Scaling (LMCS) for transforming a first pixel value space applied to a luma display image signal into a second pixel value space applied to a luma encoding process signal, using line segments forming a transform curve, each of which corresponds to a different one of sections obtained by partitioning the first pixel value space; and encodes an image, and in the performing of the LMCS, the circuitry determines the transform curve so that among boundary values in the second pixel value space, a first value obtained by dividing a boundary value by a base width defined according to a bit depth of the image is not equal to a second value obtained by dividing another boundary value by the base width.

公开(公告)号：US12244809B2

公开(公告)日：2025-03-04

申请号：US17527546

申请日：2021-11-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Yusuke Kato ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/18 ,  H04N19/46 ,  H04N19/60

Abstract: An encoder including circuitry and memory coupled to the circuitry. In both of a first case where an orthogonal transform is performed and a second case where the orthogonal transform is skipped, when a number of CABAC processes is within an allowable range, the circuitry: encodes a plurality of coefficient information flags by CABAC; and encodes a remainder value of the coefficient; and when the number of CABAC processes is not within the allowable range, the circuitry: skips the encoding of the plurality of coefficient information flags, wherein in the first case, the circuitry: converts the coefficient to a second coefficient by using a poszero value that is determined using a plurality of surrounding coefficients; and encodes a value of the second coefficient, and wherein in the second case, the circuitry: encodes the value of the coefficient.

公开(公告)号：US12238329B2

公开(公告)日：2025-02-25

申请号：US18384984

申请日：2023-10-30

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/513 ,  H04N19/86

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: derives a motion vector of a current block by referring to at least one reference picture different from a picture to which the current block belongs; performs a mode for estimating, for each sub-block unit of sub-blocks obtained by splitting the current block, a surrounding region of the motion vector to correct the motion vector; determines whether to apply deblocking filtering to each of boundaries between neighboring ones of the sub-blocks; and applies the deblocking filtering to the boundary, based on a result of the determination.

公开(公告)号：US12167007B2

公开(公告)日：2024-12-10

申请号：US17675444

申请日：2022-02-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Che-Wei Kuo ,  Hai Wei Sun ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/423 ,  H04N19/172 ,  H04N19/174 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry encodes second information indicating whether first information is present in a bitstream, the first information being regarding a subpicture which is a rectangular region in a picture, the picture including slices, and when the second information indicates that the first information is present in the bitstream, each of the slices is a rectangular slice and has a subpicture index indicating a subpicture to which the slice belongs.

公开(公告)号：US12149723B2

公开(公告)日：2024-11-19

申请号：US18368642

申请日：2023-09-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/176 ,  H04N19/70

Abstract: According to one aspect of the present disclosure, a decoder includes memory and a processor coupled to the memory. The processor is configured to split a current picture into tiles, generate a slice having a rectangular shape and located at a lower-right corner of the current picture, the slice including at least a part of a tile among the tiles, generate first information on a region of the slice with header information, the header information not including information identical to the first information, and decode the slice with the first information.

公开(公告)号：US12143639B2

公开(公告)日：2024-11-12

申请号：US17535873

申请日：2021-11-26

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/463

Abstract: An encoder includes memory and circuitry coupled to the memory. The circuitry stores a total number of temporal sub-layers in a bitstream into either a picture timing supplemental enhancement information (SEI) message or a buffering period SEI message, and encodes the total number of the temporal sub-layers.

公开(公告)号：US20240297986A1

公开(公告)日：2024-09-05

申请号：US18657222

申请日：2024-05-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Yusuke Kato ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/107 ,  H04N19/176

CPC classification number: H04N19/107 ,  H04N19/176

Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.

公开(公告)号：US12075052B2

公开(公告)日：2024-08-27

申请号：US17499294

申请日：2021-10-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/126 ,  H04N19/159 ,  H04N19/176 ,  H04N19/61

CPC classification number: H04N19/126 ,  H04N19/159 ,  H04N19/176 ,  H04N19/61

Abstract: Provided is an encoder including: circuitry; and memory coupled to the circuitry, in which the circuitry: derives a prediction residual indicating a difference between a current block and a prediction image of the current block; performs primary transform on the prediction residual, and performs secondary transform on a result of the primary transform; performs quantization on a result of the secondary transform; and encodes a result of the quantization. In the performing of the secondary transform, when a matrix weighted intra prediction included in intra prediction and having prediction modes is used, the circuitry uses, as a transform set for the secondary transform, a common transform set shared among the prediction modes. The matrix weighted intra prediction generates the prediction image by performing matrix calculation on a pixel sequence obtained from pixel values of surrounding pixels of the current block.

公开(公告)号：US12034938B2

公开(公告)日：2024-07-09

申请号：US18171242

申请日：2023-02-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: G06V10/00 ,  H04N19/126 ,  H04N19/156 ,  H04N19/159 ,  H04N19/18 ,  H04N19/52 ,  H04N19/61

CPC classification number: H04N19/159 ,  H04N19/126 ,  H04N19/156 ,  H04N19/18 ,  H04N19/52 ,  H04N19/61

Abstract: An image encoder is provided including circuitry and a memory coupled to the circuitry. The circuitry, in operation, responds to a size of a block satisfying a size condition by generating a prediction image using a prediction mode selected from a plurality of prediction modes. The plurality of prediction modes include a first prediction mode in which a prediction process uses a motion vector and a reference block in a same picture as the block. The circuitry encodes the block using the prediction image.