公开(公告)号：US20170048541A1

公开(公告)日：2017-02-16

申请号：US15339735

申请日：2016-10-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Kouji Nakajima ,  Eiji Otomura

IPC: H04N19/513 ,  H04N19/51 ,  H04N19/70 ,  H04N19/122

CPC classification number: H04N19/513 ,  H04N19/122 ,  H04N19/176 ,  H04N19/182 ,  H04N19/44 ,  H04N19/51 ,  H04N19/583 ,  H04N19/61 ,  H04N19/70

Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate an many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.

Abstract translation: 通过使用用于运动补偿的简化程序或计算装置，视频解码装置如在MPEG-4AVC标准中解码通过宏块单元上的运动检测操作压缩的视频数据。 视频解码装置将规定尺寸的压缩数据块例如16×16像素分割，生成小于块的子块，视频解码装置能够执行运动补偿操作。 视频解码装置复制分配给给定块的运动矢量以产生许多运动矢量，因为在给定块中存在子块，并且使用相应的重复运动矢量对每个子块执行运动补偿。 对每个子块的运动补偿操作产生的数据进行组合以获得与给定块对应的目标块。

公开(公告)号：US10483966B2

公开(公告)日：2019-11-19

申请号：US16226081

申请日：2018-12-19

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Takahiro Uehara ,  Takuya Ishii ,  Hiroyuki Handa ,  Atsushi Kitagawa ,  Takeshi Tanaka

IPC: H03K17/64 ,  H03K17/12 ,  H02M1/00

Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.

公开(公告)号：US10205449B2

公开(公告)日：2019-02-12

申请号：US15925104

申请日：2018-03-19

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Takahiro Uehara ,  Takuya Ishii ,  Hiroyuki Handa ,  Atsushi Kitagawa ,  Takeshi Tanaka

IPC: H03K17/64 ,  H03K17/12 ,  H02M1/00

Abstract: A switching circuit includes: a drive power supply; a first transistor and a second transistor; a drive signal source; and a drive circuit. Each of the first transistor and the second transistor includes: a drain electrode and a source electrode in which a main current flows when a corresponding one of the first transistor and the second transistor is ON; a first source terminal for passing the main current; and a second source terminal. Here, the first source terminal is connected to the source electrode at an impedance lower than an impedance of the second source terminal.

公开(公告)号：US09667972B2

公开(公告)日：2017-05-30

申请号：US14555825

申请日：2014-11-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Masaki Maeda ,  Kenjiro Tsuda ,  Masayasu Iguchi ,  Youji Shibahara

IPC: H04N7/12 ,  H04N19/139 ,  H04N19/52 ,  H04N19/176 ,  H04N19/51 ,  H04N19/61 ,  H04N19/109 ,  H04N19/137 ,  H04N19/436 ,  H04N19/105 ,  H04N19/43

CPC classification number: H04N19/139 ,  H04N19/105 ,  H04N19/109 ,  H04N19/137 ,  H04N19/176 ,  H04N19/43 ,  H04N19/436 ,  H04N19/51 ,  H04N19/52 ,  H04N19/61

Abstract: When compression encoding processing of an image is performed in units of macroblocks using a pipeline structure, an application of a skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on a structure of the pipeline stages, the motion vectors may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. This problem can be solved by (i) calculating all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selecting, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.

公开(公告)号：US09800889B2

公开(公告)日：2017-10-24

申请号：US15339735

申请日：2016-10-31

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Kouji Nakajima ,  Eiji Otomura

IPC: H04N19/70 ,  H04N19/179 ,  H04N19/182 ,  H04N19/513 ,  H04N19/51 ,  H04N19/61 ,  H04N19/44 ,  H04N19/583 ,  H04N19/122 ,  H04N19/176

CPC classification number: H04N19/513 ,  H04N19/122 ,  H04N19/176 ,  H04N19/182 ,  H04N19/44 ,  H04N19/51 ,  H04N19/583 ,  H04N19/61 ,  H04N19/70

Abstract: With use of a simplified program or calculating device for motion compensation, a video decoding device decodes video data compressed by motion detection operations on macroblock units, as in the MPEG-4AVC standard. The video decoding device splits compressed data blocks of the prescribed size, 16×16 pixels for instance, to generate sub-blocks, which are smaller than the blocks and on which the video decoding device is able to execute motion compensation operations. The video decoding device duplicates a motion vector assigned to a given block to generate an many motion vectors as there are sub-blocks in the given block, and executes motion compensation on each sub-block using the corresponding duplicate motion vector. Data resulting from the motion compensation operation on each sub-block is combined to obtain a target block corresponding to the given block.

公开(公告)号：US09641868B2

公开(公告)日：2017-05-02

申请号：US14629747

申请日：2015-02-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Takashi Hashimoto ,  Yoshiteru Hayashi

IPC: H04N19/82 ,  H04N19/51 ,  H04N19/61 ,  H04N19/117 ,  H04N19/44 ,  H04N19/43 ,  H04N19/513

CPC classification number: H04N19/82 ,  H04N19/117 ,  H04N19/43 ,  H04N19/44 ,  H04N19/513 ,  H04N19/61

Abstract: A moving image decoding apparatus which enables reduction in the memory bandwidth and the memory access latency for the motion compensation filter coefficients for use in inter-picture prediction involving motion compensation using variable coefficients includes: a decoding unit (101) which decodes, from a coded stream, a plurality of motion compensation filter coefficients; a memory (109) for holding the motion compensation filter coefficients included in the coded stream; a filter coefficient storage unit (103) for holding at least one of the motion compensation filter coefficients which is required for the motion compensation; a motion compensation unit (107) which performs motion compensation using the required motion compensation filter coefficient held in the filter coefficient storage unit; and a filter coefficient transfer control unit (102) which writes, in the memory, the motion compensation filter coefficients decoded by the decoding unit, and transfers the required motion compensation filter coefficient from the memory to the filter coefficient storage unit, only when the required coefficient is not yet stored therein.