公开(公告)号：US09667972B2

公开(公告)日：2017-05-30

申请号：US14555825

申请日：2014-11-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Amano ,  Takeshi Tanaka ,  Masaki Maeda ,  Kenjiro Tsuda ,  Masayasu Iguchi ,  Youji Shibahara

IPC: H04N7/12 ,  H04N19/139 ,  H04N19/52 ,  H04N19/176 ,  H04N19/51 ,  H04N19/61 ,  H04N19/109 ,  H04N19/137 ,  H04N19/436 ,  H04N19/105 ,  H04N19/43

CPC classification number: H04N19/139 ,  H04N19/105 ,  H04N19/109 ,  H04N19/137 ,  H04N19/176 ,  H04N19/43 ,  H04N19/436 ,  H04N19/51 ,  H04N19/52 ,  H04N19/61

Abstract: When compression encoding processing of an image is performed in units of macroblocks using a pipeline structure, an application of a skip mode or the like according to MPEG4AVC to compression encode an encoding target block requires motion vectors and the like of adjacent blocks of the encoding target block. However, depending on a structure of the pipeline stages, the motion vectors may not be determined. In such cases, the skip mode cannot be applied to compression encode the encoding target block. This problem can be solved by (i) calculating all motion information candidates, of the encoding target block, corresponding to all motion information selectable by a previous block of the encoding target block, and (ii) selecting, as the motion information of the encoding target block in the skip mode, the motion information corresponding to the motion information determined for the previous block.

公开(公告)号：US09319698B2

公开(公告)日：2016-04-19

申请号：US14499903

申请日：2014-09-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Amano ,  Masayasu Iguchi

IPC: G06K9/36 ,  H04N19/177 ,  H04N19/176 ,  H04N19/61 ,  H04N19/44 ,  H04N19/436 ,  H04N19/55 ,  H04N19/107 ,  H04N19/85

CPC classification number: H04N19/177 ,  H04N19/107 ,  H04N19/176 ,  H04N19/436 ,  H04N19/44 ,  H04N19/55 ,  H04N19/61 ,  H04N19/85

Abstract: To provide an image decoding apparatus that suppresses overhead of parallel processing to improve parallelization efficiency and reduce circuit costs, while solving neighboring macroblock dependencies. The image decoding apparatus (100) includes first and second decoding circuits (101, 102) having a transfer unit that transfers right neighborhood information or left neighborhood information, and first and second transfer completion detection units (104, 105) that respectively detect whether or not the left neighborhood information or the right neighborhood information has been transferred to the first and second decoding circuits (101, 102). Each of the first and second decoding circuits (101, 102) decodes a decoding target macroblock positioned at an edge of a region, when the transfer of the left neighborhood information or the right neighborhood information is detected. A boundary line between regions is orthogonal to a decoding direction corresponding to an order in which macroblocks adjacent to each other are sequentially decoded.

Abstract translation: 提供抑制并行处理的开销以提高并行化效率并降低电路成本的图像解码装置，同时解决相邻的宏块依赖性。 图像解码装置（100）包括具有传送右邻域信息或左邻域信息的传送单元的第一和第二解码电路（101,102），以及第一和第二传送完成检测单元（104,105），其分别检测是否 不是左邻域信息或右邻域信息已被传送到第一和第二解码电路（101,102）。 当检测到左邻居信息或右邻域信息的传送时，第一和第二解码电路（101,102）中的每一个解码位于区域边缘的解码目标宏块。 区域之间的边界线与对应于彼此相邻的宏块顺序解码的顺序的解码方向正交。