公开(公告)号：US20180182341A1

公开(公告)日：2018-06-28

申请号：US15901386

申请日：2018-02-21

Applicant: Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Yoshihiro IMAJO ,  Kazunori INOUE ,  Kenta ENDO

IPC: G09G3/36

Abstract: A drive circuit includes an output circuit provided in a display panel to output a gate-on voltage and a gate-off voltage to a plurality of gate lines. The plurality of gate lines include first to sixth gate lines sequentially disposed in a scanning direction. A first transistor is put into an on state to electrically connect the first gate line and the third gate line, a second transistor is put into the on state to electrically connect the second gate line and the fourth gate line, the third transistor is put into the on state to electrically connect the third gate line and the fifth gate line, and the fourth transistor is put into the on state to electrically connect the fourth gate line and the sixth gate line, after the output circuit outputs the gate-on voltage to the first to fourth gate line.

公开(公告)号：US20180130438A1

公开(公告)日：2018-05-10

申请号：US15864836

申请日：2018-01-08

Applicant: Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Yoshihiro IMAJO ,  Masahiro ISHII ,  Kenta ENDO ,  Tetsuo FUKAMI

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3685 ,  G09G3/20 ,  G09G3/36 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2320/02 ,  G09G2320/0223 ,  G11C19/28

Abstract: A driving circuit including an output circuit that outputs a signal to a lead line electrically connected to a signal line provided in a display panel; and an output transistor that is provided in the output circuit and connected to an output terminal of the output circuit. An on-resistance value of the output transistor is set according to a resistance value of the lead line electrically connected to the output transistor.

公开(公告)号：US20200175937A1

公开(公告)日：2020-06-04

申请号：US16783883

申请日：2020-02-06

Applicant: Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Yoshihiro IMAJO ,  Kazunori INOUE ,  Kenta ENDO

IPC: G09G3/36 ,  G09G3/20

Abstract: A drive circuit includes an output circuit provided in a display panel to output a gate-on voltage and a gate-off voltage to a plurality of gate lines. The plurality of gate lines include first to sixth gate lines sequentially disposed in a scanning direction. A first transistor is put into an on state to electrically connect the first gate line and the third gate line, a second transistor is put into the on state to electrically connect the second gate line and the fourth gate line, the third transistor is put into the on state to electrically connect the third gate line and the fifth gate line, and the fourth transistor is put into the on state to electrically connect the fourth gate line and the sixth gate line, after the output circuit outputs the gate-on voltage to the first to fourth gate line.

公开(公告)号：US20190392762A1

公开(公告)日：2019-12-26

申请号：US16442558

申请日：2019-06-17

Applicant: Panasonic Liquid Crystal Display Co., Ltd.

Inventor： Tetsuya KAWAMURA ,  Yoshihiro IMAJO

IPC: G09G3/3258 ,  H01L27/12

Abstract: A display device comprising: a first substrate; and a first TFT array and a second TFT array that are formed on the first substrate, wherein the first TFT array includes: a plurality of first gate lines extending in a first direction; and a plurality of first source lines extending in a second direction intersecting the first direction, the second TFT array includes: a plurality of second gate lines extending in one of the first direction and the second direction; and a plurality of second source lines extending in the other of the first direction and the second direction, and the first TFT array and the second TFT array are electrically isolated from each other, and disposed adjacent to each other in the first direction.