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公开(公告)号:US20180286329A1
公开(公告)日:2018-10-04
申请号:US15475176
申请日:2017-03-31
Applicant: Panasonic Liquid Crystal Display Co., Ltd.
Inventor: Kenta ENDO
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G3/3688 , G09G2300/0823 , G09G2320/041
Abstract: A liquid crystal display (LCD) may be described. The LCD can include a source driver; data lines electrically connected to the source driver; switches; connecting lines; a charge share line connecting each switch; a charge share connecting signal emitter that turns each switch on or off via the charge share line; and a thermal sensor that is secured to the LCD apparatus and detects a temperature. Each data line electrically connects to at least one of an LCD pixel, each connecting line electrically connects each pair of the data lines and each connecting line is switched on or off by each switch, the charge share connecting signal emitter turns each switch on and off in each horizontal period when the thermal sensor detects that the temperature is lower than a first predetermined temperature, and the source driver inputs a writing voltage to the plurality of data lines by column inversion.
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公开(公告)号:US20180130438A1
公开(公告)日:2018-05-10
申请号:US15864836
申请日:2018-01-08
Applicant: Panasonic Liquid Crystal Display Co., Ltd.
Inventor: Yoshihiro IMAJO , Masahiro ISHII , Kenta ENDO , Tetsuo FUKAMI
CPC classification number: G09G3/3685 , G09G3/20 , G09G3/36 , G09G3/3677 , G09G2310/0286 , G09G2320/02 , G09G2320/0223 , G11C19/28
Abstract: A driving circuit including an output circuit that outputs a signal to a lead line electrically connected to a signal line provided in a display panel; and an output transistor that is provided in the output circuit and connected to an output terminal of the output circuit. An on-resistance value of the output transistor is set according to a resistance value of the lead line electrically connected to the output transistor.
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公开(公告)号:US20200175937A1
公开(公告)日:2020-06-04
申请号:US16783883
申请日:2020-02-06
Applicant: Panasonic Liquid Crystal Display Co., Ltd.
Inventor: Yoshihiro IMAJO , Kazunori INOUE , Kenta ENDO
Abstract: A drive circuit includes an output circuit provided in a display panel to output a gate-on voltage and a gate-off voltage to a plurality of gate lines. The plurality of gate lines include first to sixth gate lines sequentially disposed in a scanning direction. A first transistor is put into an on state to electrically connect the first gate line and the third gate line, a second transistor is put into the on state to electrically connect the second gate line and the fourth gate line, the third transistor is put into the on state to electrically connect the third gate line and the fifth gate line, and the fourth transistor is put into the on state to electrically connect the fourth gate line and the sixth gate line, after the output circuit outputs the gate-on voltage to the first to fourth gate line.
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公开(公告)号:US20180286326A1
公开(公告)日:2018-10-04
申请号:US15475171
申请日:2017-03-31
Applicant: Panasonic Liquid Crystal Display Co., Ltd.
Inventor: Kenta ENDO , Kazuhiko TSUDA
CPC classification number: G09G3/3607 , G09G3/006 , G09G2300/023 , G09G2330/10
Abstract: An apparatus and method for a liquid crystal display (LCD). The LCD can include a first LCD panel, a second LCD panel stacked on the first LCD panel, and a data processor that generates, based on an external input image signal, a first image data for the first LCD panel and a second image data for the second LCD panel. The data processor may further include a memory storing a position of a defective pixel of a white spot and a controller changing a gray scale level of a first pixel using the position of the defective pixel, the first pixel at least partially overlapping the position of the defective pixel, wherein the defective pixel is in the first LCD panel and the first pixel is in the second LCD panel.
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公开(公告)号:US20180182341A1
公开(公告)日:2018-06-28
申请号:US15901386
申请日:2018-02-21
Applicant: Panasonic Liquid Crystal Display Co., Ltd.
Inventor: Yoshihiro IMAJO , Kazunori INOUE , Kenta ENDO
IPC: G09G3/36
Abstract: A drive circuit includes an output circuit provided in a display panel to output a gate-on voltage and a gate-off voltage to a plurality of gate lines. The plurality of gate lines include first to sixth gate lines sequentially disposed in a scanning direction. A first transistor is put into an on state to electrically connect the first gate line and the third gate line, a second transistor is put into the on state to electrically connect the second gate line and the fourth gate line, the third transistor is put into the on state to electrically connect the third gate line and the fifth gate line, and the fourth transistor is put into the on state to electrically connect the fourth gate line and the sixth gate line, after the output circuit outputs the gate-on voltage to the first to fourth gate line.
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