公开(公告)号：US20170109090A1

公开(公告)日：2017-04-20

申请号：US14885797

申请日：2015-10-16

Applicant: QUALCOMM INCORPORATED

Inventor： DEXTER TAMIO CHUN ,  YANRU LI ,  ALEXANDER GANTMAN

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/06

CPC classification number: G06F3/0625 ,  G06F3/064 ,  G06F3/0673 ,  G06F12/0292 ,  G06F12/0607 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/20 ,  G06F2212/65 ,  Y02D10/13

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels. The memory address map comprises one or more interleaved blocks and a plurality of linear blocks. Each interleaved block comprises an interleaved address space for relatively higher performance tasks, and each linear block comprises a linear address space for relatively lower power tasks. A request is received from a process for a virtual memory page. The request comprises a preference for power savings or performance. If the preference is for power savings, the virtual memory page is mapped to a physical page in a concatenated linear block.