公开(公告)号：US20140226395A1

公开(公告)日：2014-08-14

申请号：US13767788

申请日：2013-02-14

Applicant: QUALCOMM INCORPORATED

Inventor： Ramaprasath Vilangudipitchai ,  Gaurav Bhargava ,  Ohsang Kwon

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C2207/007

Abstract: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

Abstract translation: 基于锁存器的存储器包括以行和列排列的多个从锁存器。 每列从锁存器从相应的主锁存器接收锁存的数据信号。 每行包括时钟门控电路和相应的复位电路。 如果一行对于写操作有效，则活动行的时钟选通电路将写时钟传递到活动行的从锁存器。 相反，用于非活动行的时钟门控电路通过将第一时钟状态的写入时钟的保持版本传递到非活动行的从锁存器来将写时钟门禁到非活动行的从锁存器。 当复位信号被断言时，每个复位电路通过将第一时钟状态下的写入时钟的保持版本传送到复位电路行中的从锁存器来对写时钟进行门控。

公开(公告)号：US08971098B1

公开(公告)日：2015-03-03

申请号：US14023382

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Gaurav Bhargava ,  Ramaprasath Vilangudipitchai ,  Ohsang Kwon

IPC: G11C11/00 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/10 ,  G11C29/022 ,  G11C29/32

Abstract: A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.

Abstract translation: 基于闩锁的阵列包括多个列和行。 每列包括多个从锁存器，它们在正常操作期间并行地从锁存器的主锁存器输出的主锁存数据并行锁存。 在故障测试操作模式下，列中的一个从站锁存主锁存数据输出的反向版本，而列中剩余的从锁存器锁存主锁存数据输出。 以这种方式，从锁存器在单次写入操作中被去相关。

公开(公告)号：US08848429B2

公开(公告)日：2014-09-30

申请号：US13767788

申请日：2013-02-14

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Gaurav Bhargava ,  Ohsang Kwon

IPC: G11C11/00 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C2207/007

Abstract: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

Abstract translation: 基于锁存器的存储器包括以行和列排列的多个从锁存器。 每列从锁存器从相应的主锁存器接收锁存的数据信号。 每行包括时钟门控电路和相应的复位电路。 如果一行对于写操作有效，则活动行的时钟选通电路将写时钟传递到活动行的从锁存器。 相反，用于非活动行的时钟门控电路通过将第一时钟状态的写入时钟的保持版本传递到非活动行的从锁存器来将写时钟门禁到非活动行的从锁存器。 当复位信号被断言时，每个复位电路通过将第一时钟状态下的写入时钟的保持版本传送到复位电路行中的从锁存器来对写时钟进行门控。

公开(公告)号：US20150070973A1

公开(公告)日：2015-03-12

申请号：US14023382

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Gaurav Bhargava ,  Ramaprasath Vilangudipitchai ,  Ohsang Kwon

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/10 ,  G11C29/022 ,  G11C29/32

Abstract: A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.

Abstract translation: 基于闩锁的阵列包括多个列和行。 每列包括多个从锁存器，它们在正常操作期间并行地从锁存器的主锁存器输出的主锁存数据并行锁存。 在故障测试操作模式下，列中的一个从站锁存主锁存数据输出的反向版本，而列中剩余的从锁存器锁存主锁存数据输出。 以这种方式，从锁存器在单次写入操作中被去相关。