公开(公告)号：US09948303B2

公开(公告)日：2018-04-17

申请号：US15367751

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03L5/00 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/01855 ,  H03K19/0963

Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

公开(公告)号：US09859893B1

公开(公告)日：2018-01-02

申请号：US15367706

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K3/35 ,  H03K19/00 ,  G09G3/20 ,  H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356113 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/0013

Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

公开(公告)号：US09673787B2

公开(公告)日：2017-06-06

申请号：US14861503

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Jeffrey Gemar ,  Ramaprasath Vilangudipitchai

IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/037 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/3562

Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

公开(公告)号：US20160248414A1

公开(公告)日：2016-08-25

申请号：US14818114

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

IPC: H03K17/042 ,  H03K5/24

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Abstract translation: 本文描述了为电路供电的系统和方法。 在一个实施例中，一种用于上电的方法包括将第一电源轨的电压与第二电源轨的电压进行比较，以及确定第一电源轨的电压是否在第二电源轨的电压的预定量内 至少基于该比较的预定时间段。 该方法还包括在确定第一电源轨的电压在第二电源轨的电压的预定量内至少在预定时间段内的情况下，启动耦合在第一和第二电源轨之间的多个开关的开关 时间。

公开(公告)号：US09178496B2

公开(公告)日：2015-11-03

申请号：US14605805

申请日：2015-01-26

Applicant: QUALCOMM, Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Prayag Bhanubhai Patel

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/57 ,  H03K19/00 ,  G06F1/32

CPC classification number: H03K3/012 ,  G06F1/32 ,  H03K3/57 ,  H03K19/0016

Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

Abstract translation: 一种特定的方法包括接收保持信号。 响应于接收到保持信号，该方法包括将状态信息保留在保持寄存器的非易失性级中，并将功率降低到保持寄存器的易失性级。 非易失性级可以由外部电压源供电。 挥发级可由内部电压源供电。

公开(公告)号：US20150130524A1

公开(公告)日：2015-05-14

申请号：US14605805

申请日：2015-01-26

Applicant: QUALCOMM, Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Prayag Bhanubhai Patel

IPC: H03K3/012 ,  H03K19/00

CPC classification number: H03K3/012 ,  G06F1/32 ,  H03K3/57 ,  H03K19/0016

Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

Abstract translation: 一种特定的方法包括接收保持信号。 响应于接收到保持信号，该方法包括将状态信息保留在保持寄存器的非易失性级中，并将功率降低到保持寄存器的易失性级。 非易失性级可以由外部电压源供电。 挥发级可由内部电压源供电。

公开(公告)号：US20150070973A1

公开(公告)日：2015-03-12

申请号：US14023382

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Gaurav Bhargava ,  Ramaprasath Vilangudipitchai ,  Ohsang Kwon

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/10 ,  G11C29/022 ,  G11C29/32

Abstract: A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.

Abstract translation: 基于闩锁的阵列包括多个列和行。 每列包括多个从锁存器，它们在正常操作期间并行地从锁存器的主锁存器输出的主锁存数据并行锁存。 在故障测试操作模式下，列中的一个从站锁存主锁存数据输出的反向版本，而列中剩余的从锁存器锁存主锁存数据输出。 以这种方式，从锁存器在单次写入操作中被去相关。

公开(公告)号：US11476186B2

公开(公告)日：2022-10-18

申请号：US17081720

申请日：2020-10-27

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Gudoor Reddy ,  Samrat Sinharoy ,  Smeeta Heggond ,  Anil Kumar Koduru ,  Kamesh Medisetti ,  Seung Hyuk Kang

IPC: H01L23/522 ,  H01L27/02

Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

公开(公告)号：US10109619B2

公开(公告)日：2018-10-23

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Mohammed Yousuff Shariff ,  Parissa Najdesamii ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/535 ,  H01L27/088 ,  G06F17/50 ,  H01L21/8238

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

公开(公告)号：US20170033796A1

公开(公告)日：2017-02-02

申请号：US14814409

申请日：2015-07-30

Applicant: QUALCOMM Incorporated

Inventor： Lipeng Cao ,  Divjyot Bhan ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K17/693

CPC classification number: H03K17/693 ,  H03K19/0016

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

Abstract translation: 本文公开了一种用于通过电力轨道复用进行电力管理的集成电路（IC）。 在示例方面，IC包括第一电力轨，第二电力轨和负载电力轨。 IC还包括第一组晶体管，其包括耦合到第一电力轨的第一晶体管和包括耦合到第二电力轨的第二晶体管的第二组晶体管。 IC还包括电力多路复用器电路，其被配置为通过顺序地关闭第一组晶体管的第一晶体管，然后顺序地接通第一组晶体管的第一晶体管，从而将负载电源轨从第一电力轨到第二电力轨的电​​力切换 第二组晶体管的第二晶体管。