公开(公告)号：US10600785B2

公开(公告)日：2020-03-24

申请号：US15927539

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Michael Joseph Brunolli ,  Christine Sung-An Hau-Riege ,  Mickael Malabry ,  Sucheta Kumar Harish ,  Prathiba Balasubramanian ,  Kamesh Medisetti ,  Nikolay Bomshtein ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/16 ,  H03K17/687 ,  H01L23/482 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

公开(公告)号：US20150109045A1

公开(公告)日：2015-04-23

申请号：US14059361

申请日：2013-10-21

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Ohsang Kwon ,  Srivatsan Thiruvengadam

IPC: H03K19/0185

CPC classification number: H03K19/018585 ,  H03K19/018528

Abstract: A layout architecture for voltage level shifters is provided. The architecture includes features of voltage level shifter cells and arrangements of the voltage level shifter cells within integrated circuits. The architecture can be used, for example, in CMOS system-on-a-chip integrated circuits implemented using metal-programmable standard cells. The architecture is also scalable for interfaces having different numbers of signals. The architecture can provide reduced area and improved performance.

Abstract translation: 提供了电压电平转换器的布局架构。 该架构包括电压电平移位器单元的特征和集成电路内的电压电平移位器单元的布置。 该架构可以用于例如使用金属可编程标准单元实现的CMOS片上集成电路。 该架构对于具有不同数量信号的接口也是可扩展的。 该架构可以提供面积缩小和性能提升。

公开(公告)号：US09306570B1

公开(公告)日：2016-04-05

申请号：US14603262

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Joshua Lance Puckett ,  Ohsang Kwon ,  William James Goodall, III ,  Benjamin John Bowers

IPC: H03K19/177 ,  H01L25/00 ,  H03K19/0175 ,  H03K19/20 ,  H01L27/118

CPC classification number: H03K19/017581 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11874 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/20

Abstract: At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

Abstract translation: 具有连续有源区域的至少一个可配置电路单元包括至少一个中心子电池，第一侧子电池和第二侧子电池。 每个中心子电池包括第一和第二pMOS晶体管以及第一和第二nMOS晶体管。 第一个pMOS晶体管具有第一个pMOS晶体管栅极，源极和漏极。 第一pMOS晶体管源耦合到第一电压源。 第二个pMOS晶体管具有第二个pMOS晶体管栅极，源极和漏极。 第二pMOS晶体管源耦合到第一电压源。 第一个pMOS晶体管漏极和第二个pMOS晶体管漏极是相同的漏极。 第一个nMOS晶体管具有第一nMOS晶体管栅极，源极和漏极。 第一nMOS晶体管源耦合到第二电压源。 第二nMOS晶体管具有第二nMOS晶体管栅极，源极和漏极。 第二nMOS晶体管源耦合至第二电压源。 第一nMOS晶体管漏极和第二nMOS晶体管漏极是相同的漏极。

公开(公告)号：US08971098B1

公开(公告)日：2015-03-03

申请号：US14023382

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Gaurav Bhargava ,  Ramaprasath Vilangudipitchai ,  Ohsang Kwon

IPC: G11C11/00 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/10 ,  G11C29/022 ,  G11C29/32

Abstract: A latch-based array includes a plurality of columns and rows. Each column comprises a plurality of slave latches that all latch in parallel a master-latched data output from the column's master latch during normal operation. In a fault-testing mode of operation, one of the slaves in the column latches an inverted version of the master-latched data output while the remaining slave latches in the column latch the master-latched data output. In this fashion, the slave latches are decorrelated in a single write operation.

Abstract translation: 基于闩锁的阵列包括多个列和行。 每列包括多个从锁存器，它们在正常操作期间并行地从锁存器的主锁存器输出的主锁存数据并行锁存。 在故障测试操作模式下，列中的一个从站锁存主锁存数据输出的反向版本，而列中剩余的从锁存器锁存主锁存数据输出。 以这种方式，从锁存器在单次写入操作中被去相关。

公开(公告)号：US08848429B2

公开(公告)日：2014-09-30

申请号：US13767788

申请日：2013-02-14

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Gaurav Bhargava ,  Ohsang Kwon

IPC: G11C11/00 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C2207/007

Abstract: A latch-based memory includes a plurality of slave latches arranged in rows and columns. Each column of slave latches receives a latched data signal from a corresponding master latch. Each row includes a clock gating circuit and a corresponding reset circuit. If a row is active for a write operation, the active row's clock gating circuit passes a write clock to the active row's slave latches. Conversely, the clock gating circuit for an inactive row gates the write clock to the inactive row's slave latches by passing a held version of the write clock in a first clock state to the inactive row's slave latches. While a reset signal is asserted, each reset circuit gates the write clock by passing the held version of the write clock in the first clock state to the slave latches in the reset circuit's row.

Abstract translation: 基于锁存器的存储器包括以行和列排列的多个从锁存器。 每列从锁存器从相应的主锁存器接收锁存的数据信号。 每行包括时钟门控电路和相应的复位电路。 如果一行对于写操作有效，则活动行的时钟选通电路将写时钟传递到活动行的从锁存器。 相反，用于非活动行的时钟门控电路通过将第一时钟状态的写入时钟的保持版本传递到非活动行的从锁存器来将写时钟门禁到非活动行的从锁存器。 当复位信号被断言时，每个复位电路通过将第一时钟状态下的写入时钟的保持版本传送到复位电路行中的从锁存器来对写时钟进行门控。

公开(公告)号：US20140225655A1

公开(公告)日：2014-08-14

申请号：US13767729

申请日：2013-02-14

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H03L7/00

CPC classification number: H04L7/0331 ,  H03K5/135 ,  H04L7/0276

Abstract: Techniques for clock gating a synchronizer are described herein. In one embodiment a circuit for clock gating a synchronizer comprises a clock-gating circuit configured to receive an input clock signal, and to selectively provide either the input clock signal or a fixed clock signal to the synchronizer. The circuit also comprises a comparator configured to compare a data value of a data signal input to the synchronizer, a first value of the synchronizer, and a second value of the synchronizer with one another, to instruct the clock-gating circuit to provide the input clock signal to the synchronizer if the data value, the first value, and the second value are not all the same, and to instruct the clock-gating circuit to provide the fixed clock signal to the synchronizer if the data value, the first value, and the second value are all the same.

Abstract translation: 本文描述了用于时钟门控同步器的技术。 在一个实施例中，用于时钟门控同步器的电路包括配置成接收输入时钟信号并且选择性地向同步器提供输入时钟信号或固定时钟信号的时钟门控电路。 该电路还包括比较器，其被配置为将输入到同步器的数据信号的数据值，同步器的第一值和同步器的第二值彼此进行比较，以指示时钟门控电路提供输入 如果所述数据值，所述第一值和所述第二值不完全相同，则指示所述同步器的时钟信号，并且指示所述时钟选通电路向所述同步器提供所述固定时钟信号，如果所述数据值，所述第一值， 而第二个值都是一样的。

公开(公告)号：US10175571B2

公开(公告)日：2019-01-08

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Hyeokjin Bruce Lim ,  Ohsang Kwon ,  Mickael Malabry ,  Jingwei Zhang ,  Raymond George Stephany ,  Haining Yang ,  Kern Rim ,  Stanley Seungchul Song ,  Mukul Gupta ,  Foua Vang

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

公开(公告)号：US10074609B2

公开(公告)日：2018-09-11

申请号：US15493008

申请日：2017-04-20

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

公开(公告)号：US09379058B2

公开(公告)日：2016-06-28

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Ohsang Kwon ,  Kern Rim ,  John Jianhong Zhu ,  Xiangdong Chen ,  Foua Vang ,  Raymond George Stephany ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US09331016B2

公开(公告)日：2016-05-03

申请号：US14338229

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Esin Terzioglu ,  Hadi Bunnalim

IPC: H01L29/40 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/498 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧v2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

Abstract translation: SOC装置包括具有最小间距g的多个栅极互连，具有最小间距m的多个金属互连以及互连栅极互连和金属互连的多个通孔。 通孔具有最小间距v。值m，g和v使得g2 +m2≥2v，g和m的LCM小于20g。 SOC装置还可以包括具有最小间距m2的第二多个金属互连，其中m2> m且g，m和m2的LCM小于20g。