公开(公告)号：US20240322562A1

公开(公告)日：2024-09-26

申请号：US18188971

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Vignesh MARIYAPPAN ,  Anand Kumar KALAIRAJ ,  Prashanth Kumar KAKKIRENI ,  Amit DAS

IPC: H02J1/00 ,  H02J7/00 ,  H02J7/34 ,  H02M1/00 ,  H02M3/158

CPC classification number: H02J1/001 ,  H02J7/0068 ,  H02J7/345 ,  H02M1/0045 ,  H02M3/158 ,  H02J7/0048

Abstract: Techniques and apparatus for swapping a primary power source (e.g., a main battery) while using a secondary power source (e.g., a backup battery or a supercapacitor) to power a portable device. One example integrated circuit (IC) for power management generally includes a first power supply node; a second power supply node; a first port for coupling to a primary power source; a first switch coupled between the first power supply node and the first port; a second port for coupling to a secondary power source; a second switch coupled between the first power supply node and the second port; and a third switch coupled between the first and second power supply nodes. For certain aspects, the IC also includes a third power supply node, a voltage regulator coupled between the first and third power supply nodes, and a fourth switch coupled between the second and third power supply nodes.

公开(公告)号：US20250103092A1

公开(公告)日：2025-03-27

申请号：US18476111

申请日：2023-09-27

Applicant: QUALCOMM INCORPORATED

Inventor： Prashanth Kumar KAKKIRENI ,  Naveen Kumar NARALA ,  Amod PHADKE ,  Arun GOTHEKAR ,  Anirudh GHAYAL

IPC: G06F1/10 ,  G06F1/3287 ,  G06F15/78

Abstract: A global count or reference time in a computing device may be maintained during a sleep state in which the global counter is powered off. The global count from the global counter may be saved in a register when the sleep state is entered. When the sleep state is exited, the global count in the register may be restored in the global counter.

公开(公告)号：US20250132560A1

公开(公告)日：2025-04-24

申请号：US19005813

申请日：2024-12-30

Applicant: QUALCOMM Incorporated

Inventor： Vignesh MARIYAPPAN ,  Anand Kumar KALAIRAJ ,  Prashanth Kumar KAKKIRENI ,  Amit DAS

IPC: H02J1/00 ,  H02J7/00 ,  H02J7/34 ,  H02M1/00 ,  H02M3/158

Abstract: Techniques and apparatus for swapping a primary power source (e.g., a main battery) while using a secondary power source (e.g., a backup battery or a supercapacitor) to power a portable device. One example integrated circuit (IC) for power management generally includes a first power supply node; a second power supply node; a first port for coupling to a primary power source; a first switch coupled between the first power supply node and the first port; a second port for coupling to a secondary power source; a second switch coupled between the first power supply node and the second port; and a third switch coupled between the first and second power supply nodes. For certain aspects, the IC also includes a third power supply node, a voltage regulator coupled between the first and third power supply nodes, and a fourth switch coupled between the second and third power supply nodes.

公开(公告)号：US20240211021A1

公开(公告)日：2024-06-27

申请号：US18069537

申请日：2022-12-21

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar KAKKIRENI ,  Matthew SEVERSON ,  Ravi JENKAL ,  Gordon LEE ,  Kevin Bradley CITTERELLE ,  Ronald ALTON ,  Anish MUTTREJA

IPC: G06F1/3296

CPC classification number: G06F1/3296

Abstract: Various embodiments include power management system methods including receiving, at a processor(s), a notification signal triggering the processor(s) to implement power usage mitigation at the processor(s), determining, by the processor(s), a mitigation amount of power rail power by which to mitigate current usage at a power rail based on a use case for the power rail, and implementing power usage mitigation at the processor(s) by the processor(s) sufficient to mitigate power usage at the power rail by the mitigation amount of power rail power. Power usage mitigation may include reducing processor(s) current usage: by a predefined amount; proportional to the amount a power rail current exceeds a power rail current threshold; by the amount of current exceeding a processor current threshold; or by a smallest amount between the amount a power rail current exceeds a power rail current threshold and the processor(s) current exceeds a processor current threshold.

公开(公告)号：US20220413593A1

公开(公告)日：2022-12-29

申请号：US17359350

申请日：2021-06-25

Applicant: QUALCOMM Incorporated

Inventor： Prashanth Kumar KAKKIRENI ,  Matthew SEVERSON ,  Kumar Kanti GHOSH ,  Shishir JOSHI

IPC: G06F1/3296 ,  H04L12/10

Abstract: Various embodiments may include methods and systems for power management of multiple chiplets within a system-on-a-chip (SoC). Various systems may include a power management integrated circuit (PMIC) configured to supply power to a first chiplet and a second chiplet across a shared power rail. The first chiplet may be configured to obtain first sensory information throughout the first chiplet. The second chiplet may be configured to obtain second sensory information throughout the second chiplet, and may be configured to transmit a voltage change message to the first chiplet based on the second sensory information. The first chiplet may be configured to transmit a power rail adjustment message to the PMIC based on the first sensory information and the voltage change message. The PMIC may be configured to adjust the voltage of at least one of the first chiplet and the second chiplet.

公开(公告)号：US20220222112A1

公开(公告)日：2022-07-14

申请号：US17148314

申请日：2021-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok DIBBAD ,  Bharat Kumar RANGARAJAN ,  Prashanth Kumar KAKKIRENI ,  Srinivas TURAGA

IPC: G06F9/48 ,  G06F9/52 ,  G06F1/28

Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.