公开(公告)号：US20230058318A1

公开(公告)日：2023-02-23

申请号：US17404919

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Udayakiran Kumar YALLAMARAJU ,  Xia LI ,  Pankaj DESHMUKH ,  Vajram GHANTASALA ,  Bin YANG ,  Vishal MISHRA ,  Bharatheesha Sudarshan JAGIRDAR ,  Arun Sundaresan IYER ,  Amod PHADKE ,  Vanamali BHAT

IPC: H03K5/156 ,  H03K5/134

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

公开(公告)号：US20250103092A1

公开(公告)日：2025-03-27

申请号：US18476111

申请日：2023-09-27

Applicant: QUALCOMM INCORPORATED

Inventor： Prashanth Kumar KAKKIRENI ,  Naveen Kumar NARALA ,  Amod PHADKE ,  Arun GOTHEKAR ,  Anirudh GHAYAL

IPC: G06F1/10 ,  G06F1/3287 ,  G06F15/78

Abstract: A global count or reference time in a computing device may be maintained during a sleep state in which the global counter is powered off. The global count from the global counter may be saved in a register when the sleep state is entered. When the sleep state is exited, the global count in the register may be restored in the global counter.

公开(公告)号：US20250155916A1

公开(公告)日：2025-05-15

申请号：US18509245

申请日：2023-11-14

Applicant: QUALCOMM Incorporated

Inventor： Vanamali BHAT ,  Amod PHADKE ,  Sina DENA ,  Michael TIPTON ,  Amit ANEJA ,  Prachin Sheshrao BHOYAR

IPC: G06F1/08 ,  B60W50/06

Abstract: A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.

公开(公告)号：US20240396551A1

公开(公告)日：2024-11-28

申请号：US18324785

申请日：2023-05-26

Applicant: QUALCOMM Incorporated

Inventor： Amod PHADKE ,  Vinay Kumar GARIPELLI ,  Naveen Kumar NARALA ,  Manjunath Kachenahalli RANGEGOWDA ,  Ravi Shankar SRINIVASAN

IPC: H03K19/003 ,  H03K19/096 ,  H03K19/20

Abstract: A glitch filtering circuit has a counting circuit configured to provide one or more counter output signals indicating whether an input signal has remained in a first signaling state or in a second signaling state for a preconfigured duration of time; a flipflop clocked by a clock signal and configured to provide an output of the glitch filtering circuit; a threshold detect circuit configured to generate a select signal based on the one or more counter output signals; and a multiplexer configured to provide a multiplexed signal to an input of the flipflop, the multiplexed signal having a signaling state that is selected in accordance with the select signal from an input fixed at the first signaling state, an input fixed at the second signaling state and an input that is coupled to the output of the glitch filtering circuit.