公开(公告)号：US20240113986A1

公开(公告)日：2024-04-04

申请号：US17937495

申请日：2022-10-03

Applicant: QUALCOMM Incorporated

Inventor： Narasimha Rao KORAMUTLA ,  Arun GOTHEKAR ,  Susheel Kumar Yadav YADAGIRI ,  Akshat GUPTA ,  Srinivas MARAKALA ,  Naveen Kumar NARALA ,  Radvajesh MUNIBYRAIAH

IPC: H04L47/62 ,  H04L47/2416 ,  H04L47/28 ,  H04L65/65 ,  H04L69/22

CPC classification number: H04L47/624 ,  H04L47/2416 ,  H04L47/28 ,  H04L65/65 ,  H04L69/22

Abstract: Various embodiments include an automobile network device that includes a descriptor sorting engine (DSE). The DSE may include a direct memory access (DMA) controller, a memory organized by channel clusters that each include a plurality of first-in first-out (FIFO) memories, a timer, and a time stamp (TS) sorting logic component. The DMA controller may be configured to pull timestamp-pointer pairs from packet descriptors stored in an unsorted descriptor ring memory, store the timestamp-pointer pairs in the FIFO memories, trigger the TS sorting logic component to reorder the timestamp-pointer pairs in the FIFO memories so that they are sorted in ascending order, use the sorted timestamp-pointer pairs in the FIFO memories to read the packet descriptors stored in an unsorted descriptor ring memory, and store the packet descriptors in a sorted descriptor ring memory.

公开(公告)号：US20230046542A1

公开(公告)日：2023-02-16

申请号：US17402884

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar NARALA ,  Matthew Severson ,  Haobo Zhao

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/3206 ,  G06F13/20

Abstract: Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

公开(公告)号：US20240396551A1

公开(公告)日：2024-11-28

申请号：US18324785

申请日：2023-05-26

Applicant: QUALCOMM Incorporated

Inventor： Amod PHADKE ,  Vinay Kumar GARIPELLI ,  Naveen Kumar NARALA ,  Manjunath Kachenahalli RANGEGOWDA ,  Ravi Shankar SRINIVASAN

IPC: H03K19/003 ,  H03K19/096 ,  H03K19/20

Abstract: A glitch filtering circuit has a counting circuit configured to provide one or more counter output signals indicating whether an input signal has remained in a first signaling state or in a second signaling state for a preconfigured duration of time; a flipflop clocked by a clock signal and configured to provide an output of the glitch filtering circuit; a threshold detect circuit configured to generate a select signal based on the one or more counter output signals; and a multiplexer configured to provide a multiplexed signal to an input of the flipflop, the multiplexed signal having a signaling state that is selected in accordance with the select signal from an input fixed at the first signaling state, an input fixed at the second signaling state and an input that is coupled to the output of the glitch filtering circuit.

公开(公告)号：US20210406207A1

公开(公告)日：2021-12-30

申请号：US16910194

申请日：2020-06-24

Applicant: QUALCOMM Incorporated

Inventor： Naveen Kumar NARALA

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/372 ,  G06F9/32

Abstract: Various embodiments include methods and systems performed by a processor of a first function block for providing secure timer synchronization with a second function block. Various embodiments may include storing, in a shared register space, a first time counter value in which the first time counter value is based on a global counter of the second function block, transmitting, from the shared register space, the stored first time counter value to a preload register of the first function block, receiving, by the first function block, a strobe signal from the second function block configured to enable the first time counter value in the preload register to be loaded into a global counter of the first function block, and configuring the global counter with the first time counter value from the preload register.

公开(公告)号：US20250103092A1

公开(公告)日：2025-03-27

申请号：US18476111

申请日：2023-09-27

Applicant: QUALCOMM INCORPORATED

Inventor： Prashanth Kumar KAKKIRENI ,  Naveen Kumar NARALA ,  Amod PHADKE ,  Arun GOTHEKAR ,  Anirudh GHAYAL

IPC: G06F1/10 ,  G06F1/3287 ,  G06F15/78

Abstract: A global count or reference time in a computing device may be maintained during a sleep state in which the global counter is powered off. The global count from the global counter may be saved in a register when the sleep state is entered. When the sleep state is exited, the global count in the register may be restored in the global counter.

公开(公告)号：US20230350841A1

公开(公告)日：2023-11-02

申请号：US17923110

申请日：2021-04-16

Applicant: QUALCOMM Incorporated

Inventor： Sharon GRAIF ,  Navdeep MER ,  Naveen Kumar NARALA ,  Sriharsha CHAKKA

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/4072

Abstract: Systems, methods, and apparatus are configured to enable a receiver to provide feedback. In one example, a method performed at a device coupled to a serial bus includes receiving a write command from the serial bus in a datagram, writing a data byte received in a first data frame of the datagram to a register address identified by the datagram, and using a second data frame of the datagram to provide feedback regarding the datagram. Feedback may be provided by driving a data line of the serial bus to provide a negative acknowledgement during the second data frame when a transmission error is detected in the datagram, and refraining from driving the data line of the serial bus during the second data frame when no transmission error is detected in the datagram, thereby providing an acknowledgement of the datagram.