Abstract:
An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.
Abstract:
An example system for compiling a source file includes an optimizer that identifies a segment of code in a first source file as a potential optimization opportunity. The first source file includes high-level source code. The example system also includes a compiler that identifies a compilation record storing data indicating that the segment of code is an actual optimization opportunity and generates a representation of the high-level source code in accordance with the actual optimization opportunity. The data is based on a previous compilation of a second source file.
Abstract:
An example system for compiling a source file includes an optimizer that identifies a segment of code in a first source file as a potential optimization opportunity. The first source file includes high-level source code. The example system also includes a compiler that identifies a compilation record storing data indicating that the segment of code is an actual optimization opportunity and generates a representation of the high-level source code in accordance with the actual optimization opportunity. The data is based on a previous compilation of a second source file.