公开(公告)号：US20200250101A1

公开(公告)日：2020-08-06

申请号：US16269399

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： GEORGE PATSILARAS ,  Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Jeffrey Shabel ,  Simon Peter William Booth ,  Simo Petteri Kangaslampi ,  Christopher Koob ,  Wisnu Wurjantara ,  David Hansen ,  Ron Lieberman ,  Daniel Palermo ,  Colin Sharp ,  Hao Liu

IPC: G06F12/0893 ,  G06F12/06 ,  G06F3/06 ,  H03M7/30

Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.

公开(公告)号：US11016898B2

公开(公告)日：2021-05-25

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik ,  Wesley James Holland ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0868 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/1072

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US10747671B1

公开(公告)日：2020-08-18

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06T1/60 ,  G06F12/0862 ,  G06F12/1009

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US20230029696A1

公开(公告)日：2023-02-02

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US11256894B2

公开(公告)日：2022-02-22

申请号：US16703616

申请日：2019-12-04

Applicant: QUALCOMM Incorporated

Inventor： Wesley James Holland ,  Rashmi Kulkarni ,  Ling Feng Huang ,  Huang Huang ,  Jeffrey Shabel ,  Chih-Chi Cheng ,  Satish Anand ,  Songhe Cai ,  Simon Peter William Booth ,  Bohuslav Rychlik

IPC: G06K9/00 ,  G06F21/32 ,  G01N21/31 ,  H04L9/32

Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

公开(公告)号：US10061644B2

公开(公告)日：2018-08-28

申请号：US14994078

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Nhon Quach ,  Mainak Biswas ,  Pranjal Bhuyan ,  Jeffrey Shabel ,  Robert Hardacker ,  Rahul Gulati ,  Mattheus Heddes

IPC: G06F12/00 ,  G11C29/52 ,  G06F11/10 ,  G06F12/0888 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F11/1012 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/281 ,  G06F2212/401 ,  G06F2212/466

Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

公开(公告)号：US11803472B2

公开(公告)日：2023-10-31

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

CPC classification number: G06F12/084 ,  G06F1/3212 ,  G06F2212/62

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US20200250097A1

公开(公告)日：2020-08-06

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： WESLEY JAMES HOLLAND ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0862 ,  G06F12/1009 ,  G06T1/60

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US20170123897A1

公开(公告)日：2017-05-04

申请号：US14994078

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： Nhon Quach ,  Mainak Biswas ,  Pranjal Bhuyan ,  Jeffrey Shabel ,  Robert Hardacker ,  Rahul Gulati ,  Mattheus Heddes

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F11/1012 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/1056 ,  G06F2212/281 ,  G06F2212/401 ,  G06F2212/466

Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.