公开(公告)号：US12182036B2

公开(公告)日：2024-12-31

申请号：US18163446

申请日：2023-02-02

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Engin Ipek ,  Goran Goran ,  Hamza Omar ,  Bohuslav Rychlik ,  Jeffrey Gemar ,  Matthew Severson ,  Andrew Edmund Turner

IPC: G06F12/126 ,  G06F12/0888

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

公开(公告)号：US11681624B2

公开(公告)日：2023-06-20

申请号：US16931490

申请日：2020-07-17

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  Bohuslav Rychlik ,  George Patsilaras

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/10

CPC classification number: G06F12/0815 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/657

Abstract: Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

公开(公告)号：US20200250101A1

公开(公告)日：2020-08-06

申请号：US16269399

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： GEORGE PATSILARAS ,  Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Jeffrey Shabel ,  Simon Peter William Booth ,  Simo Petteri Kangaslampi ,  Christopher Koob ,  Wisnu Wurjantara ,  David Hansen ,  Ron Lieberman ,  Daniel Palermo ,  Colin Sharp ,  Hao Liu

IPC: G06F12/0893 ,  G06F12/06 ,  G06F3/06 ,  H03M7/30

Abstract: An intelligent tile-based memory bandwidth management solution executed by an address aperture, such as a compression address aperture, services linearly addressed data requests (read requests and write requests) from a processor to data stored in a memory component having a tile-based address structure. For read requests, the aperture stores previously read tiles (full or partial) in a tile-aware cache and then seeks to service future read requests from the cache instead of the long-term memory component. For write requests, the aperture stores the write data in the tile-aware cache and assembles the data with write data from other write requests so that full tile data writes to the long-term memory may be achieved in lieu of excessive partial-tile writes.

公开(公告)号：US10592292B2

公开(公告)日：2020-03-17

申请号：US15603863

申请日：2017-05-24

Applicant: QUALCOMM Incorporated

Inventor： Mehrdad Mohammad H. Reshadi ,  Babak Salamat ,  Gheorghe C. Cascaval ,  Mark S. Fowler ,  Andrey Ermolinskiy ,  Bohuslav Rychlik

IPC: G06F3/048 ,  G06F9/50 ,  G06F3/0481

Abstract: Systems and methods enable displaying a graphical representation of system resource usage in a resource utilization map to inform users about system resource utilization by applications and processes running on a computing device. Users may provide inputs to enable the system to adjust resource allocations based on user preferences. This may enable users to improve the overall operational performance of the device consistent with their current personal preferences by identifying applications or processes of most or least interest so the device processor to prioritize system resources accordingly. Some aspects transmit resource allocation data based on such user input to a central server to enable community based resource allocation schemes. Community based resource allocation schemes may be transmitted to computing devices for use as default or preliminary resource allocations for particular applications, websites or device operating states.

公开(公告)号：US09824015B2

公开(公告)日：2017-11-21

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/12 ,  G06F12/0846 ,  G06F12/1036 ,  G06F12/109

CPC classification number: G06F12/0848 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/50 ,  G06F2212/601 ,  G06F2212/68 ,  G06F2212/70 ,  Y02D10/13

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

公开(公告)号：US09665489B2

公开(公告)日：2017-05-30

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

公开(公告)号：US20160350222A1

公开(公告)日：2016-12-01

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/50 ,  G06F2212/601 ,  G06F2212/68 ,  G06F2212/70 ,  Y02D10/13

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract translation: 提供存储器管理单元（MMU）分区转换高速缓存以及相关设备，方法和计算机可读介质。 在这方面，在一方面，提供了包括MMU的装置。 MMU包括提供定义地址转换映射的多个转换高速缓存条目的翻译高速缓存。 所述MMU还包括分区描述符表，其提供多个分区描述符，所述分区描述符定义相应的多个分区，每个分区包括所述多个转换高速缓存条目中的一个或多个转换高速缓存条目。 MMU还包括被配置为从请求者接收存储器访问请求的分区转换电路。 分区翻译电路还被配置为确定存储器访问请求的翻译高速缓存分区标识符（TCPID），基于TCPID识别多个分区中的一个或多个分区，并且在翻译高速缓存条目上执行存储器访问请求 一个或多个分区。

公开(公告)号：US20160232091A1

公开(公告)日：2016-08-11

申请号：US14619628

申请日：2015-02-11

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  Bohuslav Rychlik ,  George Patsilaras ,  Andrew Edmund Turner ,  Anwar Quinones Rohillah

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0851 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/608 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing selecting an available shared cache memory as a victim cache. The computing device may identify a remote shared cache memory with available shared cache memory space for use as the victim cache. To select the appropriate available shared cache memory, the computing device may retrieve data for the identified remote shared cache memory or a processor cluster associated with the identified remote shared cache memory relating to a metric, such as performance speed, efficiency, or effective victim cache size. Using the retrieved data, the computing device may determine the identified remote shared cache memory to use as the victim cache and select the determined remote shared cache memory to use as the victim cache.

Abstract translation: 方面包括用于实现选择可用的共享高速缓冲存储器作为受害者高速缓存的计算设备，系统和方法。 计算设备可以使用可用的共享高速缓冲存储器空间来识别远程共享高速缓冲存储器，以用作受害者高速缓存。 为了选择适当的可用共享高速缓冲存储器，计算设备可以检索与所标识的远程共享高速缓冲存储器相关联的识别的远程共享高速缓冲存储器的数据或与所标识的远程共享高速缓冲存储器有关的诸如性能速度， 尺寸。 使用所检索的数据，计算设备可以确定所识别的远程共享高速缓冲存储器以用作受害者高速缓存，并选择确定的远程共享高速缓冲存储器以用作受害者高速缓存。

公开(公告)号：US09176572B2

公开(公告)日：2015-11-03

申请号：US13759709

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案的方法，系统和设备，用于为一组处理器计算和实施性能保证，以确保处理器不处于忙状态（例如，由于临时工作负载） 该组合时段大于超过一个处理器完成其预先计算的稳态工作量所需的预定时间量。 DCVS可以基于可变延迟来调整一个或多个处理器的频率和/或电压，以确保多处理器系统仅落后于其稳态工作负载，最多只能达到预定的最大工作量，而不管 处理器的工作频率或电压。

公开(公告)号：US20230359373A1

公开(公告)日：2023-11-09

申请号：US17661810

申请日：2022-05-03

Applicant: QUALCOMM Incorporated

Inventor： Engin Ipek ,  Hamza Omar ,  Bohuslav Rychlik ,  Saumya Ranjan Kuanr ,  Behnam Dashtipour ,  Michael Hawjing Lo ,  Jeffrey Gemar ,  Matthew Severson ,  George Patsilaras ,  Andrew Edmund Turner

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673

Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.