-
公开(公告)号：US20200042750A1
公开(公告)日：2020-02-06
申请号：US16052892
申请日：2018-08-02
Applicant: QUALCOMM Incorporated
Abstract: A storage device is pre-loaded with an access block including a list of device addresses with which the device is either permitted or not permitted to communicate over a shared bus prior to a bootloader being initiated on the device. A communication circuit is coupled to the storage device, and the circuit is adapted to: (a) obtain a first command to be transmitted over the shared bus to a first device address; (b) determine whether the first device address is in the list of device addresses in the access block; and (c) allow or prevent transmission of the first command over the shared bus based on whether the firt device address is in the list of device addresses. The list of device addresses is bypassed or ignored after the bootloader procedure is completed.
-
公开(公告)号：US20200233829A1
公开(公告)日：2020-07-23
申请号：US16254189
申请日：2019-01-22
Applicant: QUALCOMM Incorporated
Inventor： Dilin VALIPARAMBIL DIVAKAR , Christopher Kong Yee CHUN
Abstract: Systems, methods, and apparatus related to the operation of a multilane serial bus communicate the configuration of lanes used to handle a transaction over the serial bus through signaling transmitted at the commencement of the transaction. The method includes asserting a multilane bus request by initiating a pulse on a secondary data lane of the serial bus while the clock lane is idle, participating in a first bus arbitration procedure executed using the secondary data lane after the pulse is terminated, providing initial signaling on the secondary data lane after winning the first bus arbitration procedure to indicate a set of data lanes to be used during a transaction, and executing a first transaction using the set of data lanes. The set of data lanes may include the primary data lane and the secondary data lane. The initial signaling may include a sequence start condition.
-
Search Results
2
records
(took 0.017 seconds)
