公开(公告)号：US10063219B1

公开(公告)日：2018-08-28

申请号：US15663209

申请日：2017-07-28

Applicant: QUALCOMM Incorporated

Inventor： Manish Srivastava ,  Satadru Sarkar ,  Samarth Vasishtha

IPC: H03K19/0175 ,  H03K3/356 ,  H03K19/0185 ,  H03K19/003 ,  H03K19/094

CPC classification number: H03K3/356113 ,  H03K19/00315 ,  H03K19/018521 ,  H03K19/09429

Abstract: Aspects of the disclosure are directed to a voltage level shifter architecture, including a voltage level shifter with circuitry residing within a footprint; and an internal augmented voltage generator residing within the footprint, wherein the internal augmented voltage generator is coupled to the voltage level shifter to augment a voltage level shift.

公开(公告)号：US10038429B1

公开(公告)日：2018-07-31

申请号：US15683691

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Qi Ye ,  Manish Srivastava ,  Venugopal Boynapalli

IPC: H03K3/3562 ,  H03K3/013 ,  H03K3/356

CPC classification number: H03K3/35625 ,  H03K3/013 ,  H03K3/356139

Abstract: A flip-flop is provided that includes a sense-amplifier-based master latch clocked by a first edge of a delayed version of a clock signal. A slave latch includes a cross-coupled pair of logic gates for latching a data output signal responsive to a second edge of the clock signal.