公开(公告)号：US20200065247A1

公开(公告)日：2020-02-27

申请号：US16113185

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Niket CHOUDHARY ,  David Scott RAY ,  Thomas Philip SPEIER ,  Eric ROBINSON ,  Harold Wade CAIN, III ,  Nikhil Narendradev SHARMA ,  Joseph Gerald MCDONALD ,  Brian Michael STEMPEL ,  Garrett Michael DRAPALA

IPC: G06F12/0862 ,  G06F12/0811

Abstract: An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

公开(公告)号：US20200065260A1

公开(公告)日：2020-02-27

申请号：US16113141

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Pritha GHOSHAL ,  Niket CHOUDHARY ,  Ravi RAJAGOPALAN ,  Patrick EIBL ,  Brian STEMPEL ,  David Scott Ray ,  Thomas Philip SPEIER

IPC: G06F12/1027

Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.

公开(公告)号：US20200065006A1

公开(公告)日：2020-02-27

申请号：US16113120

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Luke YEN ,  Niket CHOUDHARY ,  Pritha GHOSHAL ,  Thomas Philip SPEIER ,  Brian Michael STEMPEL ,  William James MCAVOY ,  Patrick EIBL

IPC: G06F3/06 ,  G06F12/0815

Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.