公开(公告)号：US20200065006A1

公开(公告)日：2020-02-27

申请号：US16113120

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Luke YEN ,  Niket CHOUDHARY ,  Pritha GHOSHAL ,  Thomas Philip SPEIER ,  Brian Michael STEMPEL ,  William James MCAVOY ,  Patrick EIBL

IPC: G06F3/06 ,  G06F12/0815

Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

公开(公告)号：US20180089094A1

公开(公告)日：2018-03-29

申请号：US15274644

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Robert Douglas CLANCY ,  Gaurav MEHTA ,  Spencer Ellis WILLIAMS ,  Brian Michael STEMPEL ,  Thomas Philip SPEIER ,  Michael Scott MCILVAINE ,  William James MCAVOY

IPC: G06F12/0891 ,  G06F12/0895 ,  G06F12/1045

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/1063 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/452 ,  G06F2212/608 ,  G06F2212/683

Abstract: Systems and methods for precise invalidation of cache lines of a virtually indexed virtually tagged (VIVT) cache include associating, with each cache line of the VIVT cache, at least a translation lookaside buffer (TLB) index corresponding to a TLB entry which comprises a virtual address to physical address translation for the cache line. The TLB entries are inclusive of the cache lines of the VIVT cache. Upon receiving an invalidate instruction, the invalidate instruction is filtered at the TLB to determine if the invalidate instruction might affect cache lines in the VIVT cache. If the invalidate instruction might affect cache lines in the VIVT cache, the TLB indices of the TLB entries which match the invalidate instruction are determined, and only the cache lines of the VIVT cache which are associated with the affected TLB indices are selectively invalidated.