公开(公告)号：US20190332385A1

公开(公告)日：2019-10-31

申请号：US15963126

申请日：2018-04-26

Applicant: QUALCOMM Incorporated

Inventor： Rodney Wayne SMITH ,  Raghavan MADHAVAN ,  Luke YEN ,  Shivam PRIYADARSHI ,  Yusuf Cagatay TEKMEN

IPC: G06F9/38

Abstract: In certain aspects of the disclosure, an apparatus comprises a first scheduling pool associated with a first minimum scheduling latency and a second scheduling pool associated with a second minimum scheduling latency, the second minimum scheduling latency greater than the first minimum scheduling latency. A common instruction picker is coupled to both the first scheduling pool and the second scheduling pool. The common instruction picker may be configured to select a first instruction from the first scheduling pool and a second instruction from the second scheduling pool, and then choose either the first instruction or second instruction for dispatch according to a picking policy.

公开(公告)号：US20200065006A1

公开(公告)日：2020-02-27

申请号：US16113120

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Luke YEN ,  Niket CHOUDHARY ,  Pritha GHOSHAL ,  Thomas Philip SPEIER ,  Brian Michael STEMPEL ,  William James MCAVOY ,  Patrick EIBL

IPC: G06F3/06 ,  G06F12/0815

Abstract: A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

公开(公告)号：US20190155608A1

公开(公告)日：2019-05-23

申请号：US16193935

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Arthur PERAIS ,  Michael Scott MCILVAINE ,  Rami Mohammad A. AL SHEIKH ,  Robert Douglas CLANCY ,  Luke YEN ,  Rodney Wayne SMITH

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

Abstract: Aspects of the present disclosure include a method, a device, and a computer-readable medium for restarting an instruction pipeline of a processor that includes a decoupled fetcher. A method comprises detecting, in a processor, a re-fetch event, wherein the processor includes an instruction unit (IU) configured to fetch instructions from a decoupled fetcher (DCF), and simultaneously flushing the IU and the DCF in response to detecting of the re-fetch event.

公开(公告)号：US20170046158A1

公开(公告)日：2017-02-16

申请号：US14827245

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Luke YEN ,  Michael William MORROW ,  Thomas Philip SPEIER ,  James Norris DIEFFENDERFER

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/383

Abstract: Systems and methods for identifying candidate load instructions for prefetch operations based on at least instruction encoding of the load instructions, include an identifier based on a function of at least one or more fields of a load instruction and optionally, a subset of bits of the PC value of the load instruction, wherein the one or more fields exclude a full address or program counter (PC) value of the load instruction. Prefetch mechanisms, including a prefetch table indexed by the identifier, can determine whether the load instruction is a candidate load instruction for prefetching load data, based on the identifier. The function may be a hash, a concatenation, or a combination thereof, of one or more bits of the one or more fields. The fields include one or more of a base register, a destination register, an immediate offset, an offset register, or other bits of instruction encoding of the load instruction.

Abstract translation: 用于基于至少指令编码加载指令来识别用于预取操作的候选加载指令的系统和方法包括基于加载指令的至少一个或多个字段的功能的标识符，以及可选地，PC的位的子集 值，其中一个或多个字段排除加载指令的完整地址或程序计数器（PC）值。 预取机制，包括由标识符索引的预取表，可以基于标识符来确定加载指令是否是用于预取负载数据的候选加载指令。 该功能可以是一个或多个字段的一个或多个比特的散列，连接或其组合。 这些字段包括基本寄存器，目的地寄存器，立即偏移量，偏移寄存器或加载指令的指令编码的其他位中的一个或多个。