公开(公告)号：US20200019229A1

公开(公告)日：2020-01-16

申请号：US16033014

申请日：2018-07-11

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra SRINIVAS ,  Abhijit JOSHI ,  Bharat KAVALA ,  Abinash ROY

IPC: G06F1/32 ,  G06F1/28

Abstract: Systems and methods for power sequencing include, for an integrated circuit comprising one or more logic instances, one or more power multiplexers to select from at least a first power rail and a second power rail, an active power rail to supply power to the one or more logic instances. One or more sequence multiplexers are used to choose from at least a first power sequence for the first power rail and a second power sequence for the second power rail, an active power sequence. One or more head switches coupled to the one or more logic instances are either turned on, in the active power sequence, to supply power to the one or more logic instances from the active power rail, or turned off, in the active power sequence, the one or more head switches, to power down the one or more logic instances.

公开(公告)号：US20200278739A1

公开(公告)日：2020-09-03

申请号：US15929732

申请日：2020-05-19

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra SRINIVAS ,  Bharat Kumar RANGARAJAN ,  Rajesh ARIMILLI

IPC: G06F1/3296 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G11C5/14 ,  G06F1/3206 ,  G06F1/26

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

公开(公告)号：US20190265778A1

公开(公告)日：2019-08-29

申请号：US15908534

申请日：2018-02-28

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra SRINIVAS ,  Bharat Kumar RANGARAJAN ,  Rajesh ARIMILLI

IPC: G06F1/32

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

公开(公告)号：US20200264788A1

公开(公告)日：2020-08-20

申请号：US16277668

申请日：2019-02-15

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra SRINIVAS ,  Kaustav ROYCHOWDHURY ,  Siddesh HALAVARTHI MATH REVANA

IPC: G06F3/06 ,  G06F12/084

Abstract: Systems and methods for memory power management may receive a wake up event in retention mode that may be used to control three memory sequencers that wake up respective groups of memory sequencers.