公开(公告)号：US20150109025A1

公开(公告)日：2015-04-23

申请号：US14057782

申请日：2013-10-18

Applicant: Qualcomm Incorporated

Inventor： Saravanan MARIMUTHU ,  Sakthivel PACKIRISAMY ,  Vijayalakshmi RANGANNA

IPC: H03K19/0948 ,  H01L23/532 ,  H03K19/094 ,  H01L27/092

CPC classification number: H03K19/0948 ,  H01L27/0207 ,  H01L27/092 ,  H03K19/09425

Abstract: A CMOS device includes a PMOS transistor and an NMOS transistor. The CMOS device further includes a poly interconnect connecting together a drain of the PMOS transistor and a drain of the NMOS transistor. The poly interconnect may be located on an edge of a standard cell including the device. The CMOS device may further include a first interconnect on an MD layer connecting the drain of the PMOS transistor to the poly interconnect, and a second interconnect on the MD layer connecting the drain of the NMOS transistor to the poly interconnect. The PMOS transistor and the NMOS transistor may operate as a CMOS inverter. The CMOS device may be a tristate inverter, and specifically, a tristate inverter within a latch array.

Abstract translation: CMOS器件包括PMOS晶体管和NMOS晶体管。 CMOS器件还包括将PMOS晶体管的漏极和NMOS晶体管的漏极连接在一起的多晶硅互连。 多晶硅互连可以位于包括该器件的标准电池的边缘上。 CMOS器件还可以包括在连接PMOS晶体管的漏极和多晶硅互连的MD层上的第一互连，以及连接NMOS晶体管的漏极和多晶硅互连的MD层上的第二互连。 PMOS晶体管和NMOS晶体管可以作为CMOS反相器工作。 CMOS器件可以是三态反相器，具体地说，是锁存器阵列内的三态反相器。

公开(公告)号：US20140177344A1

公开(公告)日：2014-06-26

申请号：US14025741

申请日：2013-09-12

Applicant: QUALCOMM Incorporated

Inventor： Saravanan MARIMUTHU ,  Sachin BAPAT ,  Sakthivel PACKIRISAMY

IPC: G11C8/16 ,  G11C7/10

CPC classification number: G11C8/16 ,  G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/18 ,  G11C29/818 ,  G11C2207/108 ,  Y10T29/49117

Abstract: An integrated circuit element is disclosed having a memory device; a P-type semiconductor region including a first semiconductor device from a first memory port circuit coupled to the memory device and configured to enable access to the memory device when the first semiconductor device is activated; an N-type semiconductor region including a second semiconductor device from a second memory port circuit coupled to the memory device and configured to enable access to the memory device when the second semiconductor device is activated; and a plurality of signal lines distributed over the P-type and N-type semiconductor regions including a first memory port selection line coupled to allow the first semiconductor device to be activated; a second memory port selection line coupled to allow the second semiconductor device to be activated; and a clock signal line placed between the first memory port selection line and the second memory port selection line.

Abstract translation: 公开了一种具有存储器件的集成电路元件; P型半导体区域，包括耦合到存储器件的第一存储器端口电路的第一半导体器件，并且被配置为当第一半导体器件被激活时能够访问存储器件; N型半导体区域，包括耦合到所述存储器件的第二存储器端口电路的第二半导体器件，并且被配置为当所述第二半导体器件被激活时能够访问所述存储器件; 以及分布在P型和N型半导体区域上的多条信号线，包括耦合以允许第一半导体器件被激活的第一存储器端口选择线; 耦合以允许第二半导体器件被激活的第二存储器端口选择线; 以及设置在第一存储器端口选择线和第二存储器端口选择线之间的时钟信号线。