公开(公告)号：US20170207783A1

公开(公告)日：2017-07-20

申请号：US15476847

申请日：2017-03-31

申请人： Nvidia Corporation

发明人： Andreas J. GOTTERBA ,  Jesse S. WANG

IPC分类号： H03K19/00 ,  G11C7/06 ,  G11C11/419 ,  H03K3/038 ,  H03K19/094

CPC分类号： H03K19/0002 ,  G11C7/065 ,  G11C11/419 ,  H03K3/038 ,  H03K19/09425

摘要： Three state latch. In accordance with a first embodiment, an electronic circuit includes n pairs of cascaded logical gates. Each of the n pairs of cascaded logical gates includes a first logical gate including n−1 first gate inputs and one first gate output, and a second logical gate including two second gate inputs and one second gate output. One of the second gate inputs is coupled to the first gate output. The second gate output is cross coupled to one of the first gate inputs of all other the pairs of cascaded logical gates, and n is greater than 2.

公开(公告)号：US20150263729A1

公开(公告)日：2015-09-17

申请号：US14645447

申请日：2015-03-12

申请人： NINGBO UNIVERSITY

发明人： Pengjun WANG ,  Weitong TANG ,  Qian WANG

IPC分类号： H03K19/00 ,  H03K19/20 ,  H03K19/094

CPC分类号： H03K19/0013 ,  H03K19/09425 ,  H03K19/20

摘要： A carbon nanotube field-effect transistor encoder, based on a binary circuit which includes: a first inverter, a second inverter, a third inverter, a first three-input NAND gate, a second three-input NAND gate, a third three-input NAND gate, a fourth three-input NAND gate, a fifth three-input NAND gate, a sixth three-input NAND gate, a seventh three-input NAND gate, a first two-input NAND gate, a second two-input NAND gate, a third two-input NAND gate and a two-input AND gate. When the input end of the encoder inputs three-bit binary input signals, the three-bit binary input signals are first processed by the binary circuit; and the processed signals are input into the ternary circuit which includes a first CNFET NAND gate, a second CNFET NAND gate, a first CNFET NOR gate, a second CNFET NOR gate, a fourth inverter and a fifth inverter to be converted into ternary signals for transmission.

摘要翻译： 一种基于二进制电路的碳纳米管场效应晶体管编码器，包括：第一反相器，第二反相器，第三反相器，第一三输入NAND门，第二三输入NAND门，第三三输入 NAND门，第四三输入NAND门，第五三输入NAND门，第六三输入NAND门，第七三输入NAND门，第一双输入NAND门，第二双输入NAND门 ，第三个双输入NAND门和双输入AND门。 当编码器的输入端输入三位二进制输入信号时，三位二进制输入信号首先由二进制电路处理; 并且经处理的信号被输入到三元电路中，其包括第一CNFET NAND门，第二CNFET NAND门，第一CNFET或非门，第二CNFET或非门，第四反相器和第五反相器，以被转换为三元信号 传输。

公开(公告)号：US20130214814A1

公开(公告)日：2013-08-22

申请号：US13827902

申请日：2013-03-14

申请人： WAVE SEMICONDUCTOR, INC.

发明人： Gajendra Prasad Singh ,  Richard Shaw Terrill

IPC分类号： H03K19/094

CPC分类号： H03K19/094 ,  H03K19/09425

摘要： A self-ready flash null Convention Logic (NCL) gate includes a one-shot circuit to create the flash timing to reset the gate to a null state. The one-shot circuit may be any type of circuit to generate a pulse in response to a change of state of an input line. In one embodiment, the one-shot circuit may start the pulse in response to a change of a flash input line and end the pulse in response to the NCL output being reset to a null state.

摘要翻译： 一个自准备的闪存公约逻辑（NCL）门包括一个单触发电路，用于创建将门复位为零状态的闪存定时。 单触发电路可以是响应于输入线的状态的改变而产生脉冲的任何类型的电路。 在一个实施例中，单触发电路可以响应于闪速输入线的改变而启动脉冲，并且响应于NCL输出被重置为零状态而结束该脉冲。

公开(公告)号：US5917340A

公开(公告)日：1999-06-29

申请号：US946739

申请日：1997-10-08

申请人： Amar S. Manohar ,  Bor Lee

发明人： Amar S. Manohar ,  Bor Lee

IPC分类号： H03K19/003 ,  H03K19/094 ,  H03K17/16 ,  H03K17/687 ,  H03K19/0185

CPC分类号： H03K19/00361 ,  H03K19/09425

摘要： A twisted-pair current driver is implemented in CMOS. EMI from sharp changes in the current driven is reduced by gradually changing the current driven when the inputs change. The current driver is divided into N differential drivers, each driving one-Nth of the total switching current to the twisted pair. Delay lines delay when input changes are sent to each of the four differential drivers, staggering their response. Either binary or multi-level-transition (MLT-3) data can be transmitted. A binary-to-MLT converter uses a dummy flip-flop to match delays and eliminate encoding glitches. Either the binary or the MLT-3 encoded data is coupled to the inputs of the delay lines and the differential drivers. The mid-level for MLT-3 is driven when both the inputs are high, causing the differential drivers to split the current among the two differential outputs to the twisted pair. The amount of current switched by each differential driver is doubled for multi-level mode to allow receivers to observe the smaller, multiple steps.

摘要翻译： 双绞线电流驱动器在CMOS中实现。 电流驱动的急剧变化引起的EMI通过逐渐改变当输入变化时驱动的电流而减少。 目前的驱动程序分为N个差分驱动器，每个驱动器将总开关电流的十分之一驱动到双绞线。 当输入更改发送到四个差分驱动器中的每一个时，延迟线延迟，从而使其响应错开。 可以传输二进制或多级转换（MLT-3）数据。 二进制到MLT转换器使用虚拟触发器来匹配延迟并消除编码毛刺。 二进制或MLT-3编码的数据被耦合到延迟线和差分驱动器的输入端。 当两个输入均为高电平时，MLT-3的中间电平被驱动，导致差分驱动器将两个差分输出之间的电流分配到双绞线。 每个差分驱动器切换的电流量对于多电平模式是加倍的，以允许接收机观察较小的多个步骤。

公开(公告)号：US5479114A

公开(公告)日：1995-12-26

申请号：US329161

申请日：1994-10-26

申请人： Tadahiko Miura

发明人： Tadahiko Miura

IPC分类号： H03K19/20 ,  H03K17/30 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948 ,  H03K19/00

CPC分类号： H03K17/302 ,  H03K19/09425

摘要： A 3-value input buffer circuit is configured by a first N-channel MOS transistor whose source is connected to an input terminal, a first P-channel MOS transistor which is connected to the first N-channel MOS transistor, a first inverter whose input is connected to a drain of the first P-channel MOS transistor, a second P-channel MOS transistor whose source is connected to the input terminal, a second N-channel MOS transistor which is connected to the second P-channel MOS transistor, a second inverter which is connected to a drain of the second N-channel MOS transistor, and a voltage applying circuit which is constituted by P-channel MOS transistors and which applies a constant voltage to a gate of each of the first N-channel MOS transistor and the second P-channel MOS transistor. The first N-channel MOS transistor and the second P-channel MOS transistor are cut off when the input terminal is in an open state. Thus, the power consumption can be significantly suppressed.

摘要翻译： 3值输入缓冲电路由源极连接到输入端的第一N沟道MOS晶体管，连接到第一N沟道MOS晶体管的第一P沟道MOS晶体管，第一反向器的输入端 连接到第一P沟道MOS晶体管的漏极，源极连接到输入端的第二P沟道MOS晶体管，连接到第二P沟道MOS晶体管的第二N沟道MOS晶体管， 连接到第二N沟道MOS晶体管的漏极的第二反相器，以及由P沟道MOS晶体管构成并且施加恒定电压到第一N沟道MOS晶体管的每一个的栅极的电压施加电路 和第二P沟道MOS晶体管。 当输入端处于打开状态时，第一N沟道MOS晶体管和第二P沟道MOS晶体管截止。 因此，可以显着地抑制功耗。

公开(公告)号：US4617479B1

公开(公告)日：1993-09-21

申请号：US60701884

申请日：1984-05-03

申请人： ALTERA SEMICONDUCTOR CORP.

发明人： ROBERT F. HARTMANN ,  SAU-CHING WONG ,  YIU-FAI CHAN ,  JUNG-HSING OU

IPC分类号： H03K5/02 ,  H03K19/094 ,  H03K19/177 ,  G06F7/00 ,  H03K19/20

CPC分类号： H03K19/17712 ,  H03K5/023 ,  H03K19/09425

公开(公告)号：US4689503A

公开(公告)日：1987-08-25

申请号：US575567

申请日：1984-01-31

申请人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

发明人： Yukio Suzuki ,  Ikuro Masuda ,  Masahiro Iwamura ,  Shinji Kadono ,  Akira Uragami ,  Masayoshi Yoshimura ,  Toshiaki Matsubara

IPC分类号： H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/094 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/01 ,  H03K19/013 ,  H03K19/017

CPC分类号： H03K19/09448 ,  H03K19/017518 ,  H03K19/01806 ,  H03K19/09425 ,  H03K19/09429 ,  H01L2924/0002

摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.

摘要翻译： 在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。 因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。 类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由 双极晶体管。 因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

公开(公告)号：US4393480A

公开(公告)日：1983-07-12

申请号：US234197

申请日：1981-02-13

申请人： Hiroshi Shimada

发明人： Hiroshi Shimada

IPC分类号： G11C11/41 ,  G11C8/00 ,  G11C8/06 ,  G11C11/413 ,  G11C11/418 ,  H03K19/094 ,  G11C11/40

CPC分类号： H03K19/09425 ,  G11C11/418 ,  G11C8/00 ,  G11C8/06 ,  H03K19/09429

摘要： An address buffer circuit which generates a pair of complementary signals for selecting a memory cell according to an address input signal is disclosed. This address buffer circuit comprises a short circuit device connected between a pair of output terminals for the complementary signals. During the stand-by period of a memory, the short circuit device electrically connects the pair of output terminals, so that the potential of both of the pair of output terminals becomes an intermediate level between high and low levels provided at the output terminals during the active period of the memory.

摘要翻译： 公开了一种地址缓冲电路，其产生用于根据地址输入信号选择存储单元的一对互补信号。 该地址缓冲电路包括连接在用于互补信号的一对输出端之间的短路装置。 在存储器的待机期间，短路装置电连接一对输出端子，使得一对输出端子的电位成为在输出端子处提供的高电平和低电平之间的中间电平 活跃期的记忆。

公开(公告)号：US4100429A

公开(公告)日：1978-07-11

申请号：US752141

申请日：1976-12-20

申请人： Yoshio Adachi

发明人： Yoshio Adachi

IPC分类号： G01R19/165 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/20 ,  H03K19/08 ,  H03K3/353 ,  H03K17/18 ,  H03K19/40

CPC分类号： H03K19/018557 ,  H03K19/01855 ,  H03K19/09425 ,  H03K19/09429 ,  H03K19/20

摘要： A logic circuit in which a first switching means controlled by a first clock pulse signal and a second switching means controlled by a second clock pulse signal are connected in series with each other between the terminals of a first and a second power source, the first and the second clock pulse signals being out of phase from each other, in which an external signal having three levels is applied as an input to the junction point of the first and second switching means, the three-level signal has a first level, i.e. the voltage of the first power source, a second level, i.e. the voltage of the second power source, and an open level, and in which an output is delivered at the junction point. In the logic circuit, when the external input is at the first or the second level, an output corresponding to the input is delivered irrespective of the clock pulses; and when the external input is at the open level, the first level is delivered on the arrival of the first clock pulse while the second level is delivered on the arrival of the second clock pulse, whereby the three levels externally applied can be identified.

摘要翻译： 一种逻辑电路，其中由第一时钟脉冲信号控制的第一开关装置和由第二时钟脉冲信号控制的第二开关装置在第一和第二电源的端子之间彼此串联连接，第一和第二电源 第二时钟脉冲信号彼此异相，其中具有三个电平的外部信号作为输入施加到第一和第二开关装置的接合点，三电平信号具有第一电平，即， 第一电源的电压，第二电平，即第二电源的电压和开放电平，并且其中输出在接合点处被传送。 在逻辑电路中，当外部输入处于第一或第二电平时，不管时钟脉冲如何都输出对应于输入的输出; 并且当外部输入处于开放电平时，在第一时钟脉冲的到达时传送第一电平，同时在第二时钟脉冲的到达时传送第二电平，由此可以识别外部施加的三个电平。

公开(公告)号：US3949242A

公开(公告)日：1976-04-06

申请号：US575065

申请日：1975-05-06

申请人： Masataka Hirasawa ,  Akira Hashimoto

发明人： Masataka Hirasawa ,  Akira Hashimoto

IPC分类号： G09G3/36 ,  G02F1/133 ,  H03K5/00 ,  H03K19/094 ,  H03K19/096 ,  H03K19/20 ,  H03K19/08 ,  G08B5/36

CPC分类号： H03K19/09425

摘要： A logical circuit comprises a circuit having a plurality of insulated gate field effect transistors of different channel types and three terminals to which are connected corresponding voltage sources each having a different voltage level, and means for supplying first, second and third logical signals having the maximum and minimum voltage levels of the above-mentioned three different voltage levels to the circuit so that only one current path is always created between an output terminal of the circuit and any one of the three terminals. As a result, the logical circuit can generate an output having three logical levels.

摘要翻译： 逻辑电路包括具有不同通道类型的多个绝缘栅场效应晶体管和三个端子的电路，每个端子连接有各自具有不同电压电平的相应电压源，以及用于提供具有最大值的第一，第二和第三逻辑信号的装置 以及对电路的上述三种不同电压电平的最小电压电平，使得总是在电路的输出端子和三个端子中的任何一个之间仅产生一个电流路径。 结果，逻辑电路可以产生具有三个逻辑电平的输出。