公开(公告)号：US09349422B2

公开(公告)日：2016-05-24

申请号：US14687739

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

IPC: G11C7/22 ,  G11C29/02 ,  G06F1/10

CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ⅛ of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算与子速率频率（例如，全速率频率的1/2，¼或⅛）相关联的子速率校准状态。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

公开(公告)号：US20130290766A1

公开(公告)日：2013-10-31

申请号：US13867954

申请日：2013-04-22

Applicant: RAMBUS INC.

Inventor： Huy Nguyen ,  Vijay Gadde ,  Kambiz Kaviani ,  Thomas Giovannini ,  Todd Bystrom

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

Abstract translation: 一种源同步通信系统，其中第一集成电路（IC）向第二IC传送数据信号和伴随选通信号。 一个或两个IC支持选通通道的滞后，允许第二IC区分选通前导和噪声，从而防止数据捕获的错误触发。 还可以采用迟滞来在接收到选通后同步码之后快速地将频闪通道置于非活动状态。

公开(公告)号：US09389637B2

公开(公告)日：2016-07-12

申请号：US13867954

申请日：2013-04-22

Applicant: Rambus Inc.

Inventor： Huy Nguyen ,  Vijay Gadde ,  Kambiz Kaviani ,  Thomas Giovannini ,  Todd Bystrom

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

Abstract translation: 一种源同步通信系统，其中第一集成电路（IC）向第二IC传送数据信号和伴随选通信号。 一个或两个IC支持选通通道的滞后，允许第二IC区分选通前导和噪声，从而防止数据捕获的错误触发。 还可以采用迟滞来在接收到选通后同步码之后快速地将频闪通道置于非活动状态。

公开(公告)号：US20150310903A1

公开(公告)日：2015-10-29

申请号：US14687739

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2，1/4或1/8）相关联 频率）。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。