公开(公告)号：US20170308144A1

公开(公告)日：2017-10-26

申请号：US15589651

申请日：2017-05-08

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/32 ,  G06F5/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/4093 ,  H03L7/081 ,  G11C7/04

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US09344064B2

公开(公告)日：2016-05-17

申请号：US14808936

申请日：2015-07-24

Applicant: Rambus Inc.

Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

IPC: G01R23/02 ,  H03K3/012 ,  H03K5/26 ,  G11C7/22 ,  H03L7/24

CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

公开(公告)号：US09231731B1

公开(公告)日：2016-01-05

申请号：US13857329

申请日：2013-04-05

Applicant: Rambus Inc.

Inventor： Huy M. Nguyen ,  Kambiz Kaviani ,  Reza Navid ,  Jason Chia-Jen Wei ,  Xudong Shi ,  Scott C. Best

IPC: H03K19/094 ,  H04L1/00

CPC classification number: H04L1/0036 ,  H04L25/0276 ,  H04L25/0278

Abstract: The common-mode input voltage of a common-gate input amplifier receiving a differential signal is set in an open-loop manner by basing the bias current and/or source load impedances of the common-gate amplifier on a transmitter bias current and driving impedance. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a closed-loop manner using a feedback loop having a captured target voltage compared to the common-mode input voltage at a node of the amplifier. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a continuous time closed loop manner by sending a reference current through resistances that are multiples of a resistance used to generate the reference current.

Abstract translation: 接收差分信号的公共栅极输入放大器的共模输入电压通过基于发射极偏置电流和驱动阻抗的公共栅极放大器的偏置电流和/或源极负载阻抗，以开环方式设置 。 接收差分信号的公共栅极输入放大器的共模输入电压可以使用具有与放大器的节点处的共模输入电压相比的捕获的目标电压的反馈环路以闭环方式设置。 接收差分信号的公共栅极输入放大器的共模输入电压可以通过以参考电流的形式发送参考电流而设置为连续时间闭环方式，电阻是用于产生参考电流的电阻的倍数。

公开(公告)号：US08867595B1

公开(公告)日：2014-10-21

申请号：US13913743

申请日：2013-06-10

Applicant: Rambus Inc.

Inventor： Lei Luo ,  Barry W. Daly ,  Kambiz Kaviani ,  John Cronan Eble, III ,  John Wilson

IPC: H04B17/00 ,  H03K3/013

CPC classification number: H03K3/013 ,  G11C5/147 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  H04L25/0296 ,  H04L25/06 ,  H04L25/08

Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本上相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。

公开(公告)号：US20140101382A1

公开(公告)日：2014-04-10

申请号：US14028172

申请日：2013-09-16

Applicant: RAMBUS INC.

Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

IPC: G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

公开(公告)号：US10761587B2

公开(公告)日：2020-09-01

申请号：US16193247

申请日：2018-11-16

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06 ,  G11C7/04 ,  H03L7/081

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US20170052584A1

公开(公告)日：2017-02-23

申请号：US15248364

申请日：2016-08-26

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/32 ,  G11C7/10 ,  G06F5/06 ,  G11C7/22

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

公开(公告)号：US09431089B2

公开(公告)日：2016-08-30

申请号：US14405910

申请日：2013-06-10

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G11C8/00 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  H03L7/081 ,  G11C7/04

CPC classification number: G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F5/065 ,  G06F2205/067 ,  G11C7/04 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272 ,  H03L7/0816

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。

公开(公告)号：US20150333740A1

公开(公告)日：2015-11-19

申请号：US14808936

申请日：2015-07-24

Applicant: Rambus Inc.

Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

IPC: H03K3/012 ,  G11C7/22 ,  H03L7/24

CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。

公开(公告)号：US20140070854A1

公开(公告)日：2014-03-13

申请号：US13839059

申请日：2013-03-15

Applicant: RAMBUS INC.

Inventor： Kambiz Kaviani ,  Kashinath Prabhu ,  Brian Hing-Kit Tsang ,  Jared L. Zerbe

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G01R23/02 ,  G11C7/222 ,  H03K5/26 ,  H03L7/24

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。