公开(公告)号：US20240234262A9

公开(公告)日：2024-07-11

申请号：US18452845

申请日：2023-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Junichi NITA ,  Seiji HIRABAYASHI

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/4842

Abstract: A common lead frame can be used for both a first package and a second package and has a planar shape according to specifications of each of a first chip used in the first package and a second chip used in the second package, and a thickness of at least a part of a lead portion through which any one of a first cutting line corresponding to an outer peripheral side of the first package and a second cutting line corresponding to an outer peripheral side of the second package passes is smaller than a thickness of a lead portion through which the first cutting line and the second cutting line do not pass.

公开(公告)号：US20240136258A1

公开(公告)日：2024-04-25

申请号：US18452845

申请日：2023-08-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Junichi NITA ,  Seiji HIRABAYASHI

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/4842

Abstract: A common lead frame can be used for both a first package and a second package and has a planar shape according to specifications of each of a first chip used in the first package and a second chip used in the second package, and a thickness of at least a part of a lead portion through which any one of a first cutting line corresponding to an outer peripheral side of the first package and a second cutting line corresponding to an outer peripheral side of the second package passes is smaller than a thickness of a lead portion through which the first cutting line and the second cutting line do not pass.

公开(公告)号：US20160163698A1

公开(公告)日：2016-06-09

申请号：US15044875

申请日：2016-02-16

Applicant: Renesas Electronics Corporation

Inventor： Junichi NITA ,  Kazutaka SUZUKI ,  Takahiro KORENARI ,  Yoshimasa UCHINUMA

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/423 ,  H01L23/535

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823487 ,  H01L23/5283 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0865 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.

Abstract translation: 半导体装置包括第一区域，第一晶体管形成在第一区域的两个或更多分割区域中，第二区域，第二晶体管形成在第二区域的两个或更多个分割区域中。 第二区域的面积数大于第一区域的面积数，第一区域和第二区域的分割区域交替排列，第一晶体管的栅极焊盘和第二区域的栅极焊盘 晶体管形成在第二区域中。