公开(公告)号：US20160291894A1

公开(公告)日：2016-10-06

申请号：US15051554

申请日：2016-02-23

Applicant: Rambus Inc.

Inventor： Chi-Ming YEUNG ,  David SECKER ,  Ravindranath KOLLIPARA ,  Shajith Musaliar SIRAJUDEEN ,  Yoshie NAKABAYASHI

IPC: G06F3/06 ,  G06F13/40

CPC classification number: G06F13/4068

Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.

Abstract translation: 用于动态终止控制的系统和方法，以便在单个通道上使用增加数量的存储器模块。 在一些实施例中，六个或八个DIMM耦合到单个通道。 动态终止方案可以包括用于地址总线/命令总线的每个存储器模块上的输入总线终端（IBT）和用于数据总线的每个存储器模块的用于片上终止（ODT）的配置）的配置。

公开(公告)号：US20150309899A1

公开(公告)日：2015-10-29

申请号：US14568768

申请日：2014-12-12

Applicant: Rambus Inc.

Inventor： Steven WOO ,  David SECKER ,  Ravindranath KOLLIPARA

IPC: G06F11/20 ,  G06F11/14

CPC classification number: G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84

Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

Abstract translation: 内存系统在主要和备份数据存储的单次写入操作中启用内存镜像。 存储器系统利用包括一个或多个等待时间组的存储器通道，每个等待时间组包含与控制器具有相同信号定时的多个存储器模块。 可以将数据元素的主副本和备份副本写入通道的相同等待时间组中的两个内存模块，并在单个写入操作中。 信道的总线可以具有与等待时间组内的每个存储器模块相同的迹线长度。

公开(公告)号：US20150331817A1

公开(公告)日：2015-11-19

申请号：US14408955

申请日：2013-10-14

Applicant: Rambus Inc.

Inventor： Minghui HAN ,  Amir AMIRKHANY ,  Ravindranath KOLLIPARA ,  Ralf Michael SCHMITT

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0611 ,  G06F3/0635 ,  G06F3/0683 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1084

Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

Abstract translation: 存储器系统包括两个存储器模块和存储器控制器。 所述存储器模块至少包括对应于第一数量的存储器级别（例如一个存储器级别）的第一存储器包和对应于第二数量的存储器级别（例如，两个存储器级别）的第二存储器包，其大于第一存储器级 内存列数对于每个模块，内存包可能是不对称交错的，这样一个内存包比存储器包更远离存储器控制器。 存储器控制器经由公共数据线耦合到两个模块的存储器封装，并且生成用于控制存储器封装的片上端接（ODT）的控制信息。

公开(公告)号：US20150309529A1

公开(公告)日：2015-10-29

申请号：US14568848

申请日：2014-12-12

Applicant: Rambus Inc.

Inventor： Steven WOO ,  David SECKER ,  Ravindranath KOLLIPARA

IPC: G06F1/12

CPC classification number: G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84

Abstract: Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.

Abstract translation: 在单写操作中启用内存镜像的内存系统。 存储器系统包括可将数据元素的重复副本存储在存储器通道中的多个位置的存储器通道。 多个位置被布置在不同的存储器模块中并且相对于从存储器控制器发送的数据信号具有不同的传播时间。 在写入操作中，根据数据传播延迟来调整多个位置之间的片选，命令和地址信号的相对定时。 结果，可以响应于在单个传输事件中从存储器控制器发送的数据信号将数据元素写入多个位置。