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    TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY
    1.
    发明申请
    TRAINING AND OPERATIONS WITH A DOUBLE BUFFERED MEMORY TOPOLOGY 审中-公开
    具有双重缓冲记忆拓扑的训练和操作

    公开(公告)号：US20160314822A1

    公开(公告)日：2016-10-27

    申请号：US15071048

    申请日：2016-03-15

    Applicant: Rambus Inc.

    Inventor： Chi-Ming YEUNG ,  Yoshie NAKABAYASHI ,  Thomas GIOVANNINI ,  Henry STRACOVSKY

    IPC: G11C7/10

    CPC classification number: G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  H03K19/1778

    Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

    Abstract translation: 用于在双缓冲存储器拓扑上进行训练和执行操作（例如，读和写操作）的系统和方法。 在一些实施例中，八个DIMM耦合到单个通道。 训练和操作方案配置有定时和信令，以允许使用双缓冲存储器拓扑进行训练和操作。 在一些实施例中，双缓冲存储器拓扑在系统板（例如，主板）上包括一个或多个缓冲器。

    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
    3.
    发明申请
    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD 审中-公开

    公开(公告)号：US20200293468A1

    公开(公告)日：2020-09-17

    申请号：US16837844

    申请日：2020-04-01

    Applicant: Rambus Inc.

    Inventor： Chi-Ming YEUNG ,  Yoshie NAKABAYASHI ,  Thomas GIOVANNINI ,  Henry STRACOVSKY

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
    5.
    发明申请
    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD 有权

    公开(公告)号：US20210326279A1

    公开(公告)日：2021-10-21

    申请号：US17316586

    申请日：2021-05-10

    Applicant: Rambus Inc.

    Inventor： Chi-Ming YEUNG ,  Yoshie NAKABAYASHI ,  Thomas GIOVANNINI ,  Henry STRACOVSKY

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD
    8.
    发明申请
    MEMORY SYSTEM DESIGN USING BUFFER(S) ON A MOTHER BOARD 审中-公开
    使用BUFFER（S）在母板上的存储器系统设计

    公开(公告)号：US20160364347A1

    公开(公告)日：2016-12-15

    申请号：US15071072

    申请日：2016-03-15

    Applicant: Rambus Inc.

    Inventor： Chi-Ming YEUNG ,  Yoshie NAKABAYASHI ,  Thomas GIOVANNINI ,  Henry STRACOVSKY

    IPC: G06F13/16 ,  G06F15/78 ,  G06F15/173 ,  G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/1673 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

    Abstract translation: 一种母板拓扑，包括可操作以耦合到一个或多个通信信道以用于传达命令的处理器。 该拓扑包括将母线上的第一组两个或多个双列直插存储器模块（DIMM）和第一主数据缓冲器电耦合的第一通信信道。 该拓扑包括第二通信通道，电连接第二组两个或更多个DIMM和母板上的第二主数据缓冲器。 该拓扑包括电耦合第一主数据缓冲器，主第二数据缓冲器和处理器的第三通道。

    DYNAMIC TERMINATION SCHEME FOR MEMORY COMMUNICATION
    9.
    发明申请
    DYNAMIC TERMINATION SCHEME FOR MEMORY COMMUNICATION 审中-公开
    用于记忆通信的动态终止方案

    公开(公告)号：US20160291894A1

    公开(公告)日：2016-10-06

    申请号：US15051554

    申请日：2016-02-23

    Applicant: Rambus Inc.

    Inventor： Chi-Ming YEUNG ,  David SECKER ,  Ravindranath KOLLIPARA ,  Shajith Musaliar SIRAJUDEEN ,  Yoshie NAKABAYASHI

    IPC: G06F3/06 ,  G06F13/40

    CPC classification number: G06F13/4068

    Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.

    Abstract translation: 用于动态终止控制的系统和方法，以便在单个通道上使用增加数量的存储器模块。 在一些实施例中，六个或八个DIMM耦合到单个通道。 动态终止方案可以包括用于地址总线/命令总线的每个存储器模块上的输入总线终端（IBT）和用于数据总线的每个存储器模块的用于片上终止（ODT）的配置）的配置。

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