公开(公告)号：US20220262415A1

公开(公告)日：2022-08-18

申请号：US17668571

申请日：2022-02-10

Applicant: Rambus Inc.

Inventor： Sreeja MENON ,  Charles J. WILSON ,  Sudhir Kumar Katla SHETTY ,  Larry ARBUTHNOT ,  Nikhil Raghavendra RAO

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/42

Abstract: System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.

公开(公告)号：US20210240566A1

公开(公告)日：2021-08-05

申请号：US17051304

申请日：2019-04-29

Applicant: Rambus Inc.

Inventor： Amit KEDIA ,  Kartik Dayalal KARIYA ,  Sreeja MENON ,  Steven C. WOO

IPC: G06F11/10 ,  G06F13/40

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.

公开(公告)号：US20230273857A1

公开(公告)日：2023-08-31

申请号：US18110737

申请日：2023-02-16

Applicant: Rambus Inc.

Inventor： Amit KEDIA ,  Kartik Dayalal KARIYA ,  Sreeja MENON ,  Steven C. WOO

IPC: G06F11/10 ,  G06F13/40

CPC classification number: G06F11/1076 ,  G06F13/4027

Abstract: Multiple independent point-to-point memory channels are operated, by at least one controller, in parallel to form a wider memory channel. The memory components on these point-to-point channels include the ability to connect to multiple (e.g., 2) instances of these independent memory channels. The controller operates multiple instances of the wider channels with the memory components configured in a clamshell mode. A single memory component is also operated in clamshell mode to provide error correction code information, independently of the other wider channels, to multiple instances of the wider memory channel.