公开(公告)号：US20240037055A1

公开(公告)日：2024-02-01

申请号：US18230375

申请日：2023-08-04

申请人： Rambus Inc.

发明人： Steven C. WOO

IPC分类号： G06F13/40 ,  H01L25/065 ,  G06N3/045

CPC分类号： G06F13/4027 ,  H01L25/0652 ,  G06N3/045

摘要： Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.

公开(公告)号：US20230081231A1

公开(公告)日：2023-03-16

申请号：US17893790

申请日：2022-08-23

申请人： Rambus Inc.

发明人： Taeksang SONG ,  Steven C. WOO ,  Torsten PARTSCH

IPC分类号： G06F3/06

摘要： Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

公开(公告)号：US20230317136A1

公开(公告)日：2023-10-05

申请号：US18121246

申请日：2023-03-14

申请人： Rambus Inc.

发明人： Steven C. WOO ,  Taeksang SONG

IPC分类号： G11C11/406

CPC分类号： G11C11/40618 ,  G11C11/40611

摘要： Refresh management commands are issued to a memory device in order to cause the refresh of rows in the vicinity of one or more rows being “hammered.” These refresh management commands are each associated with respective row addresses that indicates the row(s) to be refreshed in order to mitigate the likelihood of data being corrupted by “row hammer.” In an embodiment, the refresh management commands are issued in response to a varying number of activate (ACT) commands having been issued since the last refresh management command. The row selected for a given refresh management command may be selected based on rows that have recently been activated. The selection may be based on “pools” of recently activated rows where these pools are of unequal size. The selection from a given pool may be based on algorithmic and/or random techniques.

公开(公告)号：US20220269436A1

公开(公告)日：2022-08-25

申请号：US17627478

申请日：2020-07-06

申请人： Rambus Inc.

发明人： Mark D. KELLAM ,  Steven C. WOO ,  Thomas VOGELSANG ,  John Eric LINSTADT

IPC分类号： G06F3/06

摘要： An integrated circuit that includes a set of one or more logic layers that are, when the integrated circuit is stacked in an assembly with the set of stacked memory devices, electrically coupled to a set of stacked memory devices. The set of one or more logic layers include a coupled chain of processing elements. The processing elements in the coupled chain may independently compute partial results as functions of data received, store partial results, and pass partial results directly to a next processing element in the coupled chain of processing elements. The processing elements in the chains may include interfaces that allow direct access to memory banks on one or more DRAMs in the stack. These interfaces may access DRAM memory banks via TSVs that are not used for global I/O. These interfaces allow the processing elements to have more direct access to the data in the DRAM.

公开(公告)号：US20220156204A1

公开(公告)日：2022-05-19

申请号：US17433071

申请日：2020-02-18

申请人： Rambus Inc.

发明人： Steven C. WOO ,  Torsten PARTSCH

IPC分类号： G06F13/16

摘要： A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.

公开(公告)号：US20220083224A1

公开(公告)日：2022-03-17

申请号：US17461105

申请日：2021-08-30

申请人： Rambus Inc.

发明人： Michael Raymond MILLER ,  Steven C. WOO ,  Thomas VOGELSANG

IPC分类号： G06F3/06 ,  G06F1/08

摘要： An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.

公开(公告)号：US20240272982A1

公开(公告)日：2024-08-15

申请号：US18569503

申请日：2022-06-21

申请人： Rambus Inc.

发明人： Steven C. WOO ,  Dongyun LEE

IPC分类号： G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/1004 ,  G06F11/1068

摘要： A four-channel memory module includes four independent twenty (20) data bit memory channels and dual channel memory devices. The channels of the dual channel memory are accessed independently. Thus, the four channels for accessing the memory module each access one channel of a first set and a second set of dual channel memory devices on the module. Error detection and correction codeword configurations and schemes can implement chipkill, Single symbol data correct/double symbol data detect (SSDC/DSDD). Single symbol data correct with fewer memory devices may also be implemented. Error detection and correction codeword configurations and schemes may be switched in response to detecting a failed device, signal line, or memory channel.

公开(公告)号：US20240241670A1

公开(公告)日：2024-07-18

申请号：US18427191

申请日：2024-01-30

申请人： Rambus Inc.

发明人： Thomas VOGELSANG ,  Michael Raymond MILLER ,  Steven C. WOO

IPC分类号： G06F3/06 ,  G11C7/10

CPC分类号： G06F3/0659 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/1006

摘要： An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.

公开(公告)号：US20220237126A1

公开(公告)日：2022-07-28

申请号：US17576398

申请日：2022-01-14

申请人： Rambus Inc.

发明人： Steven C. WOO ,  Christopher HAYWOOD ,  Evan Lawrence ERICKSON

IPC分类号： G06F12/1009 ,  G06F12/02 ,  G06F12/0882 ,  G06F9/455

摘要： The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.

公开(公告)号：US20220058151A1

公开(公告)日：2022-02-24

申请号：US17399694

申请日：2021-08-11

申请人： Rambus Inc.

发明人： Steven C. WOO

IPC分类号： G06F13/40 ,  G06N3/04 ,  H01L25/065

摘要： Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.