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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE 有权

    公开(公告)号：US20220301618A1

    公开(公告)日：2022-09-22

    申请号：US17837122

    申请日：2022-06-10

    Applicant: Renesas Electronics Corporation

    Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

    IPC: G11C11/417 ,  H01L27/12 ,  G11C5/14 ,  G04G21/02 ,  H01L27/092 ,  H01L27/11 ,  H04B1/3827

    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.
    A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE 有权
    半导体集成电路器件和可擦除器件

    公开(公告)号：US20160180923A1

    公开(公告)日：2016-06-23

    申请号：US14952377

    申请日：2015-11-25

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

    IPC: G11C11/417

    CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

    Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

    Abstract translation: 提供能够在实现功耗降低的同时稳定地操作的半导体器件。 半导体器件包括CPU，指定CPU的操作速度的系统控制器，P型SOTB晶体管和N型SOTB晶体管。 半导体器件设置有连接到CPU的SRAM和连接到系统控制器并且能够向P型SOTB晶体管和N型SOTB晶体管提供衬底偏置电压的衬底偏置电路。 这里，当系统控制器指定以低速操作CPU的低速模式时，衬底偏置电路将衬底偏置电压提供给P型SOTB晶体管和N型SOTB晶体管。

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