公开(公告)号：US20220301618A1

公开(公告)日：2022-09-22

申请号：US17837122

申请日：2022-06-10

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H01L27/12 ,  G11C5/14 ,  G04G21/02 ,  H01L27/092 ,  H01L27/11 ,  H04B1/3827

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.
A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

公开(公告)号：US20190244659A1

公开(公告)日：2019-08-08

申请号：US16386887

申请日：2019-04-17

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H04B1/3827 ,  H01L27/11 ,  H01L27/092 ,  H01L27/12 ,  G04G21/02 ,  G11C5/14

CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

公开(公告)号：US20170263328A1

公开(公告)日：2017-09-14

申请号：US15382646

申请日：2016-12-17

Applicant: Renesas Electronics Corporation

Inventor： Keiichi MAEKAWA ,  Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Yoshiki YAMAMOTO

IPC: G11C17/18 ,  H01L29/36 ,  G11C17/16 ,  H01L21/283 ,  H01L21/768 ,  H01L21/266 ,  H01L27/12 ,  H01L21/84

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L21/266 ,  H01L21/283 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/36

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.

公开(公告)号：US20160180923A1

公开(公告)日：2016-06-23

申请号：US14952377

申请日：2015-11-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract translation: 提供能够在实现功耗降低的同时稳定地操作的半导体器件。 半导体器件包括CPU，指定CPU的操作速度的系统控制器，P型SOTB晶体管和N型SOTB晶体管。 半导体器件设置有连接到CPU的SRAM和连接到系统控制器并且能够向P型SOTB晶体管和N型SOTB晶体管提供衬底偏置电压的衬底偏置电路。 这里，当系统控制器指定以低速操作CPU的低速模式时，衬底偏置电路将衬底偏置电压提供给P型SOTB晶体管和N型SOTB晶体管。

公开(公告)号：US20150294964A1

公开(公告)日：2015-10-15

申请号：US14751170

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd. ,  International Business Machines Corporation ,  Renesas Electronics Corporation

Inventor： Soon Yoeng TAN ,  Teck Jung TANG ,  Ian D. MELVILLE ,  Yelei Vianna YAO ,  Yasushi YAMAGATA

IPC: H01L27/02 ,  H01L21/66

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  G06F2217/66 ,  H01L22/32

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract translation: 多项目晶片包括来自不同IP所有者的多个小芯片。 采用知识产权保护措施实施不相关的小白鼠，以防止非相关知识产权拥有者的知识产权披露。

公开(公告)号：US20180158512A1

公开(公告)日：2018-06-07

申请号：US15888426

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H01L27/092 ,  H01L27/11 ,  G04G21/02 ,  G11C5/14 ,  H01L27/12 ,  H04B1/3827

CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

公开(公告)号：US20170178717A1

公开(公告)日：2017-06-22

申请号：US15449772

申请日：2017-03-03

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H04B1/3827 ,  H01L27/11 ,  G04G21/02 ,  H01L27/092 ,  H01L27/12

CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.