公开(公告)号：US20220264450A1

公开(公告)日：2022-08-18

申请号：US17177985

申请日：2021-02-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shiro KAMOHARA ,  Akira TANABE ,  Kazuya UEJIMA ,  Jun UEHARA ,  Kazuya OKUYAMA

IPC: H04W52/02 ,  G16Y20/10 ,  G16Y30/00 ,  G16Y40/35 ,  H04W84/18

Abstract: A microcomputer performs a power supply operation to a wireless communication module at a first time interval set based on a power generation amount at a lowest day power generation amount of a temperature differential power generation module. In addition, the microcomputer performs the power supply operation to a sensor at a second time interval set based on the power generation amount at the lowest day power generation amount of the temperature differential power generation module.

公开(公告)号：US20190244659A1

公开(公告)日：2019-08-08

申请号：US16386887

申请日：2019-04-17

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H04B1/3827 ,  H01L27/11 ,  H01L27/092 ,  H01L27/12 ,  G04G21/02 ,  G11C5/14

CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

公开(公告)号：US20180158512A1

公开(公告)日：2018-06-07

申请号：US15888426

申请日：2018-02-05

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H01L27/092 ,  H01L27/11 ,  G04G21/02 ,  G11C5/14 ,  H01L27/12 ,  H04B1/3827

CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

公开(公告)号：US20170178717A1

公开(公告)日：2017-06-22

申请号：US15449772

申请日：2017-03-03

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H04B1/3827 ,  H01L27/11 ,  G04G21/02 ,  H01L27/092 ,  H01L27/12

CPC classification number: G11C11/417 ,  G04G21/025 ,  G11C5/146 ,  G11C5/148 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207 ,  H04B1/385

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

公开(公告)号：US20240363750A1

公开(公告)日：2024-10-31

申请号：US18771200

申请日：2024-07-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

CPC classification number: H01L29/7838 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H03F3/45179

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20220406936A1

公开(公告)日：2022-12-22

申请号：US17897844

申请日：2022-08-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO ,  Shiro KAMOHARA

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20220301618A1

公开(公告)日：2022-09-22

申请号：US17837122

申请日：2022-06-10

Applicant: Renesas Electronics Corporation

Inventor： Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Takumi HASEGAWA ,  Nobuyuki SUGII

IPC: G11C11/417 ,  H01L27/12 ,  G11C5/14 ,  G04G21/02 ,  H01L27/092 ,  H01L27/11 ,  H04B1/3827

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption.
A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

公开(公告)号：US20200313000A1

公开(公告)日：2020-10-01

申请号：US16753949

申请日：2017-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20200309282A1

公开(公告)日：2020-10-01

申请号：US16820130

申请日：2020-03-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shiro KAMOHARA ,  Kazuya UEJIMA

IPC: F16K31/06 ,  H01F7/08 ,  H01F7/06 ,  H01F27/28 ,  H01F7/02 ,  H01F27/24

Abstract: The semiconductor device controls the first circuit for supplying/stopping the current supplied by a DC power supply to the latching solenoid consisting of a coil and a movable iron core and a permanent magnet, the current is measured based on the input from the current detection circuit. The semiconductor device includes a control circuit having a low power dissipation mode in which the leakage current is reduced, and a normal operation mode. The control circuit maintains the low power consumption mode when no current is flowing through the coil, when a current is flowing through the coil maintains the normal operation mode, further, the movable iron core It comprises a control circuit configured to detect the inflection point of the current detected by the current detection circuit when leaving the permanent magnet.

公开(公告)号：US20170263328A1

公开(公告)日：2017-09-14

申请号：US15382646

申请日：2016-12-17

Applicant: Renesas Electronics Corporation

Inventor： Keiichi MAEKAWA ,  Shiro KAMOHARA ,  Yasushi YAMAGATA ,  Yoshiki YAMAMOTO

IPC: G11C17/18 ,  H01L29/36 ,  G11C17/16 ,  H01L21/283 ,  H01L21/768 ,  H01L21/266 ,  H01L27/12 ,  H01L21/84

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L21/266 ,  H01L21/283 ,  H01L21/76895 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/36

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.