公开(公告)号：US20150365049A1

公开(公告)日：2015-12-17

申请号：US14738066

申请日：2015-06-12

Applicant: Renesas Electronics Corporation

Inventor： Osamu OZAWA ,  Soshiro NISHIOKA ,  Takashi NAKAMURA ,  Susumu ABE ,  Kazuya TANIGUCHI ,  Masaaki TANIMURA

IPC: H03B5/36 ,  H03K3/03

CPC classification number: H03B5/36 ,  G01R31/2824 ,  H03B5/366 ,  H03B2200/005 ,  H03B2201/0266 ,  H03L7/00

Abstract: A semiconductor integrated circuit device having a function to perform oscillation in combination with a crystal oscillator, includes: a first impedance element including a first external terminal coupled to one terminal of the crystal oscillator, a second external terminal coupled to the other terminal of the crystal oscillator, and first and second terminals coupled to the first and second external terminals when the oscillation is performed; a first variable capacitance circuit coupled to the first terminal of the feedback impedance element, and a configuration circuit for setting a capacitance value of the first variable capacitance circuit. A measurement signal is supplied to the second terminal of the feedback impedance element, and in response to this, the capacitance value of the first variable capacitance circuit is set by the configuration circuit based on the delay time of an observation signal generated at the first terminal with respect to the measurement signal.

Abstract translation: 具有与晶体振荡器结合进行振荡的功能的半导体集成电路器件包括：第一阻抗元件，包括耦合到晶体振荡器的一个端子的第一外部端子，耦合到晶体的另一个端子的第二外部端子 振荡器，以及当执行振荡时耦合到第一和第二外部端子的第一和第二端子; 耦合到反馈阻抗元件的第一端子的第一可变电容电路和用于设置第一可变电容电路的电容值的配置电路。 测量信号被提供给反馈阻抗元件的第二端子，并且响应于此，第一可变电容电路的电容值由配置电路基于在第一端子处产生的观测信号的延迟时间来设置 相对于测量信号。

公开(公告)号：US20170285106A1

公开(公告)日：2017-10-05

申请号：US15508168

申请日：2014-11-26

Applicant: Renesas Electronics Corporation

Inventor： Yoichi MAEDA ,  Susumu ABE ,  Yoshitaka TAKI

IPC: G01R31/3183 ,  G06F11/25 ,  G01R31/3181

CPC classification number: G01R31/318335 ,  G01R31/31721 ,  G01R31/31813 ,  G01R31/3187 ,  G06F11/25

Abstract: A semiconductor device is provided with: a first circuit; a plurality of pattern generators connected to the first circuit and each supplying a test pattern to the first circuit; a pattern-generator control circuit controlling each of the plurality of pattern generators; a pattern compressor compressing a result output from the first circuit in response to supply of the test patterns from the plurality of pattern generators; a pattern-compressor control circuit controlling the pattern compressor; and a self-diagnosis control circuit connected to the pattern-generator control circuit and the pattern-compressor control circuit, and controlling the pattern-generator control circuit such that stop timings of the test patterns differ from one another among the plurality of pattern generators.