公开(公告)号：US20140312981A1

公开(公告)日：2014-10-23

申请号：US14244800

申请日：2014-04-03

Applicant: Renesas Electronics Corporation

Inventor： Takashi NAKAMURA ,  Kosuke YAYAMA ,  Masaaki IIJIMA

IPC: H03L7/06

CPC classification number: H03L7/0991 ,  H03L1/022 ,  H03L7/00 ,  H03L7/02 ,  H03L7/06 ,  H03L7/099 ,  H03L7/16 ,  H03L7/22 ,  H03L2207/06 ,  H03L2207/50

Abstract: A frequency-locked loop circuit includes: a digital control oscillator that generates a clock; and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes: a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit and outputs the frequency control code to the digital control oscillator.

Abstract translation: 锁频环路电路包括：产生时钟的数字控制振荡器; 以及FLL控制器，其生成用于控制时钟的振荡频率的频率控制码。 FLL控制器包括：频率比较单元，其将由数字控制振荡器产生的时钟的频率与相乘的参考时钟的频率进行比较; 以及延迟码控制单元，其基于频率比较单元的比较结果生成频率控制码，使得由数字控制振荡器产生的时钟的频率与倍增的参考时钟的频率相匹配。 频率比较单元通过使用第一和第二阈值来确定时钟的频率。 延迟代码控制单元根据频率比较单元的确定产生频率控制代码，并将频率控制代码输出到数字控制振荡器。

公开(公告)号：US20160139623A1

公开(公告)日：2016-05-19

申请号：US15007842

申请日：2016-01-27

Applicant: Renesas Electronics Corporation

Inventor： Kosuke YAYAMA ,  Takashi NAKAMURA

IPC: G06F1/08

CPC classification number: G06F1/08 ,  H01C13/02 ,  H01L27/0802 ,  H01L28/20 ,  H03B5/24

Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

公开(公告)号：US20150084135A1

公开(公告)日：2015-03-26

申请号：US14494409

申请日：2014-09-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Takashi NAKAMURA ,  Tadatoshi DANNO

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/00 ,  H01L27/088

CPC classification number: H01L24/09 ,  H01L23/4824 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/085 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0605 ,  H01L2224/091 ,  H01L2224/45014 ,  H01L2224/48096 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/4847 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

Abstract translation: 源极互连和漏极互连交替地设置在多个晶体管单元之间。 一个接合线在多个点处连接到源互连。 另一个接合线在多个点处连接到源互连。 此外，一个接合线在多个点处连接到漏极互连。 此外，另一个接合线在多个点处连接到漏极互连。

公开(公告)号：US20150365049A1

公开(公告)日：2015-12-17

申请号：US14738066

申请日：2015-06-12

Applicant: Renesas Electronics Corporation

Inventor： Osamu OZAWA ,  Soshiro NISHIOKA ,  Takashi NAKAMURA ,  Susumu ABE ,  Kazuya TANIGUCHI ,  Masaaki TANIMURA

IPC: H03B5/36 ,  H03K3/03

CPC classification number: H03B5/36 ,  G01R31/2824 ,  H03B5/366 ,  H03B2200/005 ,  H03B2201/0266 ,  H03L7/00

Abstract: A semiconductor integrated circuit device having a function to perform oscillation in combination with a crystal oscillator, includes: a first impedance element including a first external terminal coupled to one terminal of the crystal oscillator, a second external terminal coupled to the other terminal of the crystal oscillator, and first and second terminals coupled to the first and second external terminals when the oscillation is performed; a first variable capacitance circuit coupled to the first terminal of the feedback impedance element, and a configuration circuit for setting a capacitance value of the first variable capacitance circuit. A measurement signal is supplied to the second terminal of the feedback impedance element, and in response to this, the capacitance value of the first variable capacitance circuit is set by the configuration circuit based on the delay time of an observation signal generated at the first terminal with respect to the measurement signal.

Abstract translation: 具有与晶体振荡器结合进行振荡的功能的半导体集成电路器件包括：第一阻抗元件，包括耦合到晶体振荡器的一个端子的第一外部端子，耦合到晶体的另一个端子的第二外部端子 振荡器，以及当执行振荡时耦合到第一和第二外部端子的第一和第二端子; 耦合到反馈阻抗元件的第一端子的第一可变电容电路和用于设置第一可变电容电路的电容值的配置电路。 测量信号被提供给反馈阻抗元件的第二端子，并且响应于此，第一可变电容电路的电容值由配置电路基于在第一端子处产生的观测信号的延迟时间来设置 相对于测量信号。