公开(公告)号：US20230402327A1

公开(公告)日：2023-12-14

申请号：US17899609

申请日：2022-08-30

Applicant: Richtek Technology Corporation

Inventor： Chin-Chin Tsai

IPC: H01L21/8234 ,  H01L27/06

CPC classification number: H01L21/823475 ,  H01L27/0629 ,  H01L21/823456

Abstract: A manufacturing method of an integrated structure of semiconductor devices having split gates includes: forming a first silicon nitride layer covering a low voltage device and a high voltage device; etching back the first silicon nitride layer by an etching process step to form a residue silicon nitride region between two adjacent low voltage gates; forming a silicon oxide layer, a second silicon nitride layer, and a metal layer; forming two split gates by an etching process step; forming a contact etch stop layer (CESL); etching the CESL by an etching process step to form plural contacts in the CESL, wherein the contact between the two adjacent low voltage gates exposes at least part of a top surface of a common low voltage source on a substrate; and forming plural conductive plugs in the plural contacts respectively, wherein each of the conductive plug fills up the corresponding contact.

公开(公告)号：US20240030297A1

公开(公告)日：2024-01-25

申请号：US18314684

申请日：2023-05-09

Applicant: Richtek Technology Corporation

Inventor： Chin-Chin Tsai ,  Han-Chung Tai ,  Yong-Zhong Hu

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/41725 ,  H01L29/42376 ,  H01L29/401

Abstract: An integrated structure of semiconductor devices having a shared contact plug includes: a first device, a second device and a shared contact plug. The first device includes a first gate having a conduction region, two spacer regions and a protection region. The two spacer regions overlay and are connected with two ends of the conductive region, respectively. The protection region overlays and is connected with the spacer region located outside a shared side of the conductive region. The second device includes a shared region, wherein the shared region is located in a semiconductor layer which is located below and outside the protection region. The shared contact plug is formed on and in contact with the conductive region and the shared region. The first gate is electrically connected with the shared region through the shared contact plug, wherein the shared contact plug overlays and is connected with the protection region.

公开(公告)号：US20230238242A1

公开(公告)日：2023-07-27

申请号：US17933126

申请日：2022-09-19

Applicant: Richtek Technology Corporation

Inventor： Chin-Chin Tsai ,  Yong-Zhong Hu

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/28229 ,  H01L29/4916 ,  H01L21/76897 ,  H01L28/88

Abstract: A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.