公开(公告)号：US20240357804A1

公开(公告)日：2024-10-24

申请号：US18757580

申请日：2024-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： MENG-SHENG CHANG ,  CHIA-EN HUANG ,  YAO-JEN YANG ,  YIH WANG

IPC: H10B20/20 ,  G06F12/14 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00

CPC classification number: H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

Abstract: A memory device includes: a substrate; a semiconductor fin over the substrate in a first direction; a first gate electrode and a second gate electrode over the substrate in a second direction, the semiconductor fin extending through the second gate electrode and terminating at the first gate electrode; a first gate dielectric layer arranged between the semiconductor fin and the first gate electrode; and a second gate dielectric layer arranged between the semiconductor fin and the second gate electrode. The second gate electrode is configured as a read transistor of a first memory cell, in which the second gate dielectric layer is kept intact, and the first gate electrode is configured as a program transistor of the first memory cell, in which an occurrence or an absence of an electrical breakdown in the first gate dielectric layer represents a binary logic state of the first memory cell.

公开(公告)号：US20240347394A1

公开(公告)日：2024-10-17

申请号：US18757060

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/66477 ,  H10B10/12

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20240321873A1

公开(公告)日：2024-09-26

申请号：US18429611

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Juneyoung PARK ,  Jaeran JANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L27/088 ,  H01L21/76895 ,  H01L21/76898 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/5226

Abstract: An integrated circuit device, including a substrate having a plurality of device regions extending in a first horizontal direction, a plurality of gate electrodes on the plurality of device regions extending in a second horizontal direction that is orthogonal to the first horizontal direction, a plurality of source/drain regions between a pair of gate electrodes adjacent to each other in the first horizontal direction among the plurality of gate electrodes, the plurality of source/drain regions being on portions of the plurality of device regions, a plurality of gate cut regions cutting the plurality of gate electrodes and extending in the first horizontal direction, and a plurality of contact structures including a plurality of contact body portions and a plurality of contact finger portions, the plurality of contact body portions filling the plurality of gate cut regions and extending in the first horizontal direction.

公开(公告)号：US12052859B2

公开(公告)日：2024-07-30

申请号：US18066290

申请日：2022-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yao-Jen Yang ,  Yih Wang

IPC: H10B20/20 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00 ,  G06F12/14

CPC classification number: H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.

公开(公告)号：US20240250003A1

公开(公告)日：2024-07-25

申请号：US18537651

申请日：2023-12-12

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Hailing Wang ,  Dylan Charles Bartle ,  Hanching Fuh ,  David Scott Whitefield ,  Paul T. DiCarlo

IPC: H01L23/482 ,  H01L21/74 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/66 ,  H01L27/02 ,  H01L27/12 ,  H01L29/10 ,  H01L29/417 ,  H01L29/786 ,  H04B1/40

CPC classification number: H01L23/482 ,  H01L21/743 ,  H01L23/4824 ,  H01L23/4825 ,  H01L23/66 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/41733 ,  H01L29/78615 ,  H01L29/78654 ,  H04B1/40 ,  H01L21/823456 ,  H01L21/82385 ,  H01L2223/6677 ,  H01L2924/1421

Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.

公开(公告)号：US12040238B2

公开(公告)日：2024-07-16

申请号：US17353394

申请日：2021-06-21

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Guillaume Alexandre Blin ,  Aniruddha B. Joshi ,  Christophe Masse

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/66 ,  H01L27/02 ,  H01L27/092 ,  H01L29/417 ,  H03K17/081 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/84 ,  H01L23/66 ,  H01L27/1203 ,  H01L29/41733 ,  H03K17/08104 ,  H01L21/823456 ,  H01L23/3121 ,  H01L24/06 ,  H01L24/48 ,  H01L27/092 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14215 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19105

Abstract: Radio-frequency (RF) switching devices having improved voltage handling capability. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first voltage handling capacity that is greater than a second voltage handling capacity corresponding to a similar stack having a substantially uniform distribution of the parameter.

公开(公告)号：US20240222371A1

公开(公告)日：2024-07-04

申请号：US18380321

申请日：2023-10-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： TSE-YAO HUANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a substrate; a peripheral gate structure including: a peripheral gate insulating layer inwardly positioned in the substrate and including a U-shaped cross-sectional profile, a peripheral work function layer positioned on the peripheral gate insulating layer and including a recess, a first peripheral interconnect layer positioned on the peripheral work function layer, a first peripheral liner layer positioned between the peripheral work function layer and the first peripheral interconnect layer, and a peripheral capping layer positioned on the first peripheral interconnect layer. The peripheral work function layer includes titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. The first peripheral liner layer includes graphene. The first peripheral interconnect layer includes tungsten, tungsten nitride, or a combination thereof.

公开(公告)号：US11978781B2

公开(公告)日：2024-05-07

申请号：US17459885

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao Cheng ,  Fang-Ting Kuo ,  Yen-Yu Chen

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/495 ,  H01L21/28176 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66545 ,  H01L27/088 ,  H01L29/4975

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

公开(公告)号：US20240105460A1

公开(公告)日：2024-03-28

申请号：US18524896

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L21/31053 ,  H01L21/30625 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/32139

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

公开(公告)号：US11935957B2

公开(公告)日：2024-03-19

申请号：US17396903

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Wei-Chin Lee ,  Shih-Hang Chiu ,  Chia-Ching Lee ,  Hsueh Wen Tsau ,  Cheng-Yen Tsai ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.