公开(公告)号：US4764484A

公开(公告)日：1988-08-16

申请号：US107572

申请日：1987-10-08

Applicant: Roy Mo

Inventor： Roy Mo

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/88 ,  H01L21/302

CPC classification number: H01L21/76879 ,  Y10S148/02 ,  Y10S148/106

Abstract: A method is disclosed for fabricating a VLSI multilevel metallization integrated circuit in which a first dielectric layer (10), a thin silicon layer (16), and then a second dielectric layer (18) are deposited on the upper surface of a substrate. A trench (20) is formed in the upper, second dielectric layer leaving a thin layer of the second dielectric layer overlying the thin silicon layer. A contact hole (26) is then etched through the central part of the thin layer of the second dielectric layer, the thin silicon layer and the first dielectric layer to the surface of the substrate. Using the remaining outer portion (24a) of the thin layer of the dielectric layer as a mask over the underlying portion of the thin silicon layer, metal (28) such as tungsten is selectively deposited into the contact hole. The remaining portion of the thin layer of the second dielectric layer is then removed and the trench is selectively filled with a metal that is in electrical contact with the metal filling the contact hole.

Abstract translation: 公开了一种用于制造VLSI多层金属化集成电路的方法，其中第一介电层（10），薄硅层（16），然后第二介电层（18）沉积在衬底的上表面上。 沟槽（20）形成在上，第二电介质层中，留下覆在薄硅层上的第二电介质层的薄层。 然后，将接触孔（26）通过第二电介质层的薄层的中心部分，薄硅层和第一介电层蚀刻到衬底的表面。 使用电介质层的薄层的剩余的外部部分（24a）作为薄硅层下面的掩模，金属（28）如钨被选择性地沉积到接触孔中。 然后去除第二电介质层的薄层的剩余部分，并且沟槽选择性地填充有与填充接触孔的金属电接触的金属。

公开(公告)号：US4948755A

公开(公告)日：1990-08-14

申请号：US378490

申请日：1989-07-11

Applicant: Roy Mo

Inventor： Roy Mo

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L21/31116 ,  H01L21/76829 ,  H01L21/76879 ,  Y10S438/97

Abstract: A method is disclosed for fabricating a semiconductor integrated circuit which includes the selective deposition of a metal, such as tungsten, into a contact opening formed in a dielectric layer, followed by the deposition of a thin silicon layer over the dielectric and metal-filled opening and the deposition of a second dielectric layer over the thin silicon layer. An opening or trench is formed in the upper second dielectric layer using the silicon as an etch stop, and a metal such as tungsten is selectively deposited to fill the trench wherever the exposed silicon is present. In one embodiment of the invention, prior to the filling of the trench, the exposed silicon is reacted with a blanket layer of a metal to form a metal silicide layer at the lower surface of the trench.

Abstract translation: 公开了一种用于制造半导体集成电路的方法，该半导体集成电路包括将诸如钨的金属选择性沉积到形成在电介质层中的接触开口中，随后在电介质和金属填充开口上沉积薄硅层 以及在薄硅层上沉积第二介电层。 使用硅作为蚀刻停止件，在上部第二电介质层中形成开口或沟槽，并且选择性地沉积诸如钨的金属以在暴露的硅存在的地方填充沟槽。 在本发明的一个实施例中，在填充沟槽之前，暴露的硅与金属的覆盖层反应，以在沟槽的下表面形成金属硅化物层。

公开(公告)号：US4933303A

公开(公告)日：1990-06-12

申请号：US384974

申请日：1989-07-25

Applicant: Roy Mo

Inventor： Roy Mo

IPC: H01L21/3205 ,  H01L21/768

CPC classification number: H01L21/7688 ,  Y10S438/951

Abstract: A process is disclosed for making a self-aligned metal (preferably tungsten) connection in an integrated circuit. A contact hole formed in a first dielectric layer on a substrate is filled with metal, after which the first dielectric layer and the metal-filled contact hole are covered with a second dielectric layer. A photoresist layer is formed over the second dielectric layer and is patterned. A trench is formed in the exposed second dielectric layer and a thin layer of silicon or a metal such as tungsten is then sputtered or evaporated to form a layer of the silicon or metal on the upper surface of the patterned photoresist and the bottom and side walls of the trench. The patterned photoresist is removed and the trench is filled with metal.

Abstract translation: 公开了用于在集成电路中制造自对准金属（优选钨）连接的方法。 形成在基板上的第一电介质层中的接触孔用金属填充，之后第一介电层和金属填充的接触孔被第二介电层覆盖。 在第二电介质层上形成光致抗蚀剂层并进行图案化。 在暴露的第二电介质层中形成沟槽，然后溅射或蒸发硅或诸如钨的金属的薄层，以在图案化光致抗蚀剂的上表面上形成硅或金属层，并且底部和侧壁 的沟槽。 去除图案化的光致抗蚀剂，并用金属填充沟槽。