公开(公告)号：US08097514B2

公开(公告)日：2012-01-17

申请号：US12565280

申请日：2009-09-23

Applicant: Charles H. Dennison ,  Trung T. Doan

Inventor： Charles H. Dennison ,  Trung T. Doan

IPC: H01L21/336

CPC classification number: H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

Abstract: A support material for a semiconductor device is processed. An opening having a width is etched into the support material for the semiconductor device using a first etch mask. A portion of the opening is etched using a second etch mask without alignment thereof to the width of the opening.

Abstract translation: 对半导体器件的支撑材料进行处理。 使用第一蚀刻掩模将具有宽度的开口蚀刻到用于半导体器件的支撑材料中。 使用第二蚀刻掩模蚀刻开口的一部分，而不对准开口的宽度。

公开(公告)号：US07871934B2

公开(公告)日：2011-01-18

申请号：US11841906

申请日：2007-08-20

Applicant: Charles H. Dennison ,  Trung T. Doan

Inventor： Charles H. Dennison ,  Trung T. Doan

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

Abstract translation: 在集成电路和器件的制造中提供用于形成垂直触点的工艺。 该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。 该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。 在形成多级金属集成电路期间，可以重复上述过程一次或多次。

公开(公告)号：US07576011B2

公开(公告)日：2009-08-18

申请号：US11747449

申请日：2007-05-11

Applicant: Chan Sun Hyun

Inventor： Chan Sun Hyun

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/76897 ,  H01L21/76832 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  Y10S438/97

Abstract: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop layer on the first etching stop layer; forming an insulating layer on the second etching stop layer; removing the insulating layer placed between the select lines, the second etching stop layer and the first etching stop layer to form a contact hole through which a portion of the semiconductor substrate is exposed; and filling the contact hole with conductive material to form a contact plug, and so the nitride layer is thinly formed and the high dielectric layer is then formed to form the etching stop layer. Due to the above, a layer stress caused by the nitride layer can be minimized, and it is possible to resolve a problem of exposing the semiconductor substrate caused by a damage of the etching stop layer.

Abstract translation: 在半导体器件中形成接触插塞的方法包括在半导体衬底上形成多条选择线和多条字线的步骤; 在选择线和字线上形成第一蚀刻停止层; 在所述第一蚀刻停止层上形成第二蚀刻停止层; 在所述第二蚀刻停止层上形成绝缘层; 去除放置在选择线，第二蚀刻停止层和第一蚀刻停止层之间的绝缘层，以形成半导体衬底的一部分暴露在其中的接触孔; 并且用导电材料填充接触孔以形成接触塞，因此氮化物层被薄形成，然后形成高电介质层以形成蚀刻停止层。 由于上述，可以使由氮化物层引起的层应力最小化，并且可以解决由于蚀刻停止层的损伤而导致的半导体衬底的暴露的问题。

公开(公告)号：US20080254612A1

公开(公告)日：2008-10-16

申请号：US12140854

申请日：2008-06-17

Applicant: Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

Inventor： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC: H01L21/4763

CPC classification number: H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, O≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract translation: 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8，O <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07396758B2

公开(公告)日：2008-07-08

申请号：US11619502

申请日：2007-01-03

Applicant: Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

Inventor： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC: H01L21/4763

CPC classification number: H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract translation: 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.08; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07022246B2

公开(公告)日：2006-04-04

申请号：US10336992

申请日：2003-01-06

Applicant: Anil K. Chinthakindi ,  Shwu-Jen Jeng ,  Michael F. Lofaro ,  Christopher M. Schnabel ,  Kenneth J. Stein

Inventor： Anil K. Chinthakindi ,  Shwu-Jen Jeng ,  Michael F. Lofaro ,  Christopher M. Schnabel ,  Kenneth J. Stein

IPC: H01L21/302

CPC classification number: H01L28/20 ,  H01L23/5223 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  Y10S438/97 ,  Y10T29/49082 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.

Abstract translation: 公开了制造MIMCAP（由金属，绝缘体，金属（MIM）的连续层形成的电容器（CAP））和同一水平的薄膜电阻器的方法。 还公开了制造相同水平的MIMCAP和薄膜电阻器的方法，以及用于BEOL（后端处理）薄膜电阻器的新颖的集成方案，使它们更接近FEOL（前端 - 线上处理）设备。

公开(公告)号：US06680259B2

公开(公告)日：2004-01-20

申请号：US10413087

申请日：2003-04-14

Applicant: Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

Inventor： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

IPC: H01L21302

CPC classification number: H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

Abstract: A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.

Abstract translation: 提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。 具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。 然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。 在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。 一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。 与硅衬底相邻的一个部分的硅氮比小于约0.8。 在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。 优选地，两个部分一起为约50至约100纳米厚。

公开(公告)号：US20030207586A1

公开(公告)日：2003-11-06

申请号：US10413087

申请日：2003-04-14

Applicant: International Business Machines Corporation

Inventor： Chung Hon Lam ,  Eric Seung Lee ,  Francis Roger White

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3185 ,  Y10S438/97

Abstract: A method for reactive ion etching of Si02 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.

Abstract translation: 提供了用于这种蚀刻中的SiO 2的反应离子蚀刻和蚀刻停止屏障的方法。 具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。 然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。 在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。 一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。 与硅衬底相邻的一个部分的硅氮比小于约0.8。 在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。 优选地，两个部分一起为约50至约100纳米厚。

公开(公告)号：US06573601B2

公开(公告)日：2003-06-03

申请号：US10136126

申请日：2002-05-01

Applicant: Charles H. Dennison ,  Trung T. Doan

Inventor： Charles H. Dennison ,  Trung T. Doan

IPC: H01L2348

CPC classification number: H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76829 ,  Y10S438/95 ,  Y10S438/97

Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

公开(公告)号：US06531783B1

公开(公告)日：2003-03-11

申请号：US08436133

申请日：1995-05-08

Applicant: Alexander Kalnitsky

Inventor： Alexander Kalnitsky

IPC: H01L2940

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  Y10S438/97

Abstract: A method is provided for depositing a silicon nitride layer to protect and isolate underlying layers during wet etching. The silicon nitride layer maintains the integrity of interconnect leads, bond pads, and die boundaries by acting as a wet etch stop. The silicon nitride layer stops the chemicals used in a wet etch from reaching underlying layers in the integrated circuit.

Abstract translation: 提供了一种沉积氮化硅层以在湿蚀刻期间保护和分离下层的方法。 氮化硅层通过充当湿蚀刻停止来保持互连引线，接合焊盘和管芯边界的完整性。 氮化硅层阻止在湿蚀刻中使用的化学品到达集成电路中的下层。