公开(公告)号：US20130341181A1

公开(公告)日：2013-12-26

申请号：US13927754

申请日：2013-06-26

申请人： SAMSUNG DISPLAY CO., LTD. ,  SAMSUNG CORNING PRECISION MATERIALS CO., LTD.

发明人： JAEWOO PARK ,  DONGJO KIM ,  DO-HYUN KIM ,  WOO-SEOK JEON ,  JUOK PARK ,  INSUNG SOHN ,  SANGWON YOON ,  GUNHYO LEE ,  YONGJIN LEE ,  YOONGYU LEE

IPC分类号： C23C14/08 ,  C23C14/34

CPC分类号： C23C14/086 ,  C23C14/34 ,  C23C14/3414

摘要： A zinc oxide (ZnO)-based sputtering target, a method of manufacturing the same, and a thin-film transistor (TFT) having a barrier layer deposited using the same. The zinc oxide-based sputtering target includes a sinter containing zinc oxide doped with gallium oxide, the content of the gallium oxide ranging, by weight, from 10 to 50 percent of the sinter, and a backing plate bonded to the rear surface of the sinter to support the sinter. The zinc oxide-based sputtering target can be subjected to direct current (DC) sputtering, and improve the contact and etching characteristics of a barrier layer that is deposited using the same.

摘要翻译： 一种基于氧化锌（ZnO）的溅射靶，其制造方法以及使用其沉积的阻挡层的薄膜晶体管（TFT）。 氧化锌系溅射靶包括掺杂有氧化镓的氧化锌烧结体，氧化镓的含量为烧结体的10〜50重量％，与烧结体后表面接合的背板 以支持烧结矿。 氧化锌系溅射靶可以进行直流（DC）溅射，并且提高使用其进行沉积的阻挡层的接触和蚀刻特性。

公开(公告)号：US20210135039A1

公开(公告)日：2021-05-06

申请号：US16887290

申请日：2020-05-29

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： WOO-SEOK JEON ,  KWANG HYUN KIM ,  HEON SIK HA

IPC分类号： H01L31/18 ,  H01L31/0224 ,  H01L27/146

摘要： A method of manufacturing a photo sensor includes forming a first conductive layer on a substrate, the first conductive layer including a metal layer and a transparent conductive oxide layer formed on the metal layer, forming a photoconductive layer on the first conductive layer, forming a second conductive layer on the photoconductive layer, forming a first photoresist pattern on the second conductive layer, etching the second conductive layer using the first photoresist pattern as an etch mask to form a second electrode, deforming the first photoresist pattern to form a second photoresist pattern, and etching the photoconductive layer and the first conductive layer using the second photoresist pattern to form a photoconductive pattern and a first electrode, respectively.

公开(公告)号：US20240263309A1

公开(公告)日：2024-08-08

申请号：US18479233

申请日：2023-10-02

申请人： Samsung Display Co., Ltd.

发明人： WOO-SEOK JEON ,  CHULMIN BAE ,  Jaehee SEO

IPC分类号： C23C16/455 ,  C23C16/52

CPC分类号： C23C16/45544 ,  C23C16/45529 ,  C23C16/52

摘要： An atomic layer deposition apparatus includes a source gas supply part that supplies multiple source gases, a source gas supply module connected to the source gas supply part, a reaction gas supply part that supplies a reaction gas, a reaction gas supply module connected to the reaction gas supply part and spaced apart from the source gas supply module in a first direction, and a first purge gas supply module disposed between the source gas supply module and the reaction gas supply module.

公开(公告)号：US20220195578A1

公开(公告)日：2022-06-23

申请号：US17516030

申请日：2021-11-01

申请人： Samsung Display Co., Ltd.

发明人： KWANGHYUN KIM ,  HEONSIK HA ,  WOO-SEOK JEON

IPC分类号： C23C14/04 ,  C23C14/08

摘要： A manufacturing method of a mask assembly includes forming a cell mask including masking patterns and a mesh frame including conductive patterns disposed to correspond to the masking patters and disposing the cell mask and the mesh frame on a mask frame. The forming the cell mask and the mesh frame includes forming a polymer layer, a conductive layer, and a hard masking layer, forming a mask pattern layer including etch patterns, and forming the cell mask and the mesh frame using the mask pattern layer.

公开(公告)号：US20230127986A1

公开(公告)日：2023-04-27

申请号：US17869152

申请日：2022-07-20

申请人： Samsung Display Co., Ltd.

发明人： WOO-SEOK JEON

IPC分类号： H01L27/32

摘要： A display panel includes a light-emitting element, and a pixel circuit electrically connected to the light-emitting element, where the pixel circuit includes a transistor. The transistor includes: a gate; a first insulating pattern overlapping the gate, and disposed under the gate; a second insulating pattern including a part disposed outside the first insulating pattern in a plan view; and a semiconductor pattern disposed under the first insulating pattern and the second insulating pattern, and overlapping the first insulating pattern and the second insulating pattern in the plan view.