公开(公告)号：US20150017748A1

公开(公告)日：2015-01-15

申请号：US14502463

申请日：2014-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Soo JI ,  Choo Ho KIM ,  Sung Hoon OH ,  Min Hwan KIM ,  Beom Seok SHIN

IPC: H01L21/66 ,  H01L33/48

CPC classification number: H01L22/14 ,  G01R31/2601 ,  G01R31/2635 ,  H01L33/48 ,  H01L2933/0033 ,  H01L2933/005 ,  Y10T29/51

Abstract: An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit.

Abstract translation: 一种用于制造发光二极管（LED）封装的装置，包括：加热单元，其将引线框架状态中的LED封装阵列加热，其中安装多个LED封装件以阵列设置在引线框架上; 测试单元，通过向由加热单元加热的LED封装阵列施加电压或电流来测试LED封装阵列中的每个LED封装的工作状态; 以及切割单元，根据测试单元的测试结果，仅将被确定为功能产品的LED封装或从引线框确定为缺陷产品的LED封装以将其去除。

公开(公告)号：US20210223315A1

公开(公告)日：2021-07-22

申请号：US17206288

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Seok SHIN ,  Jinsoo PARK

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.

公开(公告)号：US20200225284A1

公开(公告)日：2020-07-16

申请号：US16544160

申请日：2019-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Seok SHIN ,  Jinsoo PARK

IPC: G01R31/3177 ,  G01R31/317

Abstract: A system-on-chip includes a first scan register being in a first core and being closest to an input port of the first core; an inverting circuit on a feedback path of the first scan register; a second scan register in the first core; and a logic circuit on a data path between the first scan register and the second scan register. In a test mode for an AT-SPEED test of the logic circuit, the inverting circuit generates test data by inverting scan data that are output from the first scan register, the first scan register stores the test data in response to a first pulse of a clock signal, the logic circuit generates result data based on the test data that are output from the first scan register, and the second scan register stores the result data in response to a second pulse of the clock signal.