公开(公告)号：US20240289278A1

公开(公告)日：2024-08-29

申请号：US18654803

申请日：2024-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heonsoo LEE ,  Byungchul Hong ,  Junseok Park ,  Jaehun Chung

IPC: G06F12/0862 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0862 ,  G06F9/3816 ,  G06F12/0261 ,  G06F12/0646

Abstract: In some embodiments, a multi-port queueing cache includes a plurality of first ports, a plurality of second ports, a plurality of request handlers respectively coupled to the plurality of first ports, a cache storage unit coupled to the plurality of second ports, a reserve interface configured to exchange at least one address and at least one reserved cache line number, and a request interface configured to exchange the at least one reserved cache line number and at least one data. The reserve interface and the request interface are disposed between the plurality of request handlers and the cache storage unit. The cache storage unit includes a plurality of cache lines configured to store the plurality of data. The cache storage unit is configured to output a portion of the plurality of addresses, and receive a portion of the plurality of data corresponding to the portion of the plurality of addresses.

公开(公告)号：US20240185049A1

公开(公告)日：2024-06-06

申请号：US18527856

申请日：2023-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junseok Park ,  Suknam Kwon ,  Changsoo Park ,  Heonsoo Lee ,  Byungchul Hong

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/04

Abstract: A method for tiling a neural network includes obtaining input data including neural network information of the neural network; calculating a skewness of a matrix operation between a feature map and a kernel of the neural network based on the neural network information; determining that the matrix operation comprises a memory bounded operation based on the skewness of the matrix operation; tiling the feature map and the kernel based on the determination; and executing the neural network based on the tiling.

公开(公告)号：US12013786B2

公开(公告)日：2024-06-18

申请号：US18072929

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heonsoo Lee ,  Byungchul Hong ,  Junseok Park ,  Jaehun Chung

IPC: G06F12/0862 ,  G06F9/38 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0862 ,  G06F9/3816 ,  G06F12/0261 ,  G06F12/0646

Abstract: In some embodiments, a multi-port queueing cache includes a plurality of first ports, a plurality of second ports, a plurality of request handlers respectively coupled to the plurality of first ports, a cache storage unit coupled to the plurality of second ports, a reserve interface configured to exchange at least one address and at least one reserved cache line number, and a request interface configured to exchange the at least one reserved cache line number and at least one data. The reserve interface and the request interface are disposed between the plurality of request handlers and the cache storage unit. The cache storage unit includes a plurality of cache lines configured to store the plurality of data. The cache storage unit is configured to output a portion of the plurality of addresses, and receive a portion of the plurality of data corresponding to the portion of the plurality of addresses.