公开(公告)号：US20220121956A1

公开(公告)日：2022-04-21

申请号：US17245173

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonsung BAE ,  Seungho GWAK ,  Kwangrak KIM ,  Seunggun BYOUN ,  Gilwoo SONG ,  Younghoon SHIN ,  Kyungwon YUN ,  Chiyoung LEE ,  Taeyong JO

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/067 ,  H01L21/66

Abstract: A method of manufacturing a semiconductor device includes forming a pattern on a wafer, measuring a spectrum of the pattern on the wafer, with a spectral optical system, performing an analysis of the spectrum through a deep learning model for predicting pattern characteristics, the deep learning model being trained based on a domain knowledge, and evaluating the pattern on the wafer based on the analysis of the spectrum, wherein the domain knowledge includes a noise inducing factor of the spectral optical system.

公开(公告)号：US20140140026A1

公开(公告)日：2014-05-22

申请号：US14147114

申请日：2014-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Ho YOU ,  Heeseok LEE ,  Chiyoung LEE ,  Yun-Hee LEE

IPC: H05K1/18

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/48227 ,  H01L2225/107 ,  H01L2924/1515 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/18 ,  H05K1/181 ,  Y02P70/611

Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

Abstract translation: 提供了封装基板和半导体封装。 封装基板包括具有上表面和与上表面相对的下表面的主体，附接到下表面的多个外部端子，以及形成在下表面的多个外部区域中的多个凹槽 端子未连接。 半导体封装包括封装衬底，安装在半导体衬底的上表面上的半导体芯片，以及提供安装有封装衬底的区域的板，并且安装有与多个沟槽垂直对准的多个安装元件 并插入到多个槽中。