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    SEMICONDUCTOR PACKAGE FOR IMPROVING POWER INTEGRITY CHARACTERISTICS
    1.
    发明申请
    SEMICONDUCTOR PACKAGE FOR IMPROVING POWER INTEGRITY CHARACTERISTICS 有权

    公开(公告)号：US20220361339A1

    公开(公告)日：2022-11-10

    申请号：US17591734

    申请日：2022-02-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghwa KIM ,  Junso PAK ,  Heeseok LEE ,  Moonseob JEONG ,  Jisoo HWANG

    IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H05K1/02

    Abstract: A semiconductor package including a circuit board including a first wiring region, a die mounting region surrounding the first wiring region, and a second wiring region surrounding the die mounting region; a plurality of wiring balls on the first wiring region and the second wiring region and spaced apart from one another, the plurality of wiring balls including a plurality of first wiring balls on the first wiring region and a plurality of second wiring balls on the second wiring region; a die on the die mounting region, the die including a plurality of unit chips spaced apart from one another, and a die-through region corresponding to the first wiring region and exposing the first wiring balls; and a plurality of die balls on the die and the die mounting region, the plurality of die balls being spaced apart from one another and electrically coupled to the circuit board.

    SEMICONDUCTOR PACKAGE INCLUDING A DUALIZED SIGNAL WIRING STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING A DUALIZED SIGNAL WIRING STRUCTURE 有权

    公开(公告)号：US20220181288A1

    公开(公告)日：2022-06-09

    申请号：US17542667

    申请日：2021-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heejung CHOI ,  Heeseok LEE ,  Junso PAK ,  Bongwee YU

    IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10

    Abstract: A semiconductor package including: a plurality of lower pads; an upper pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first lower pad and the second lower pad are separated from each other by a minimum distance between the plurality of lower pads.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220077064A1

    公开(公告)日：2022-03-10

    申请号：US17307037

    申请日：2021-05-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Heejung CHOI ,  Heeseok LEE ,  Junghwa KIM

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

    Abstract: A semiconductor package includes: a first package including a first semiconductor chip; a second package under the first package, the second package including a second semiconductor chip; and a first interposer package between the first package and the second package, the first interposer package including: a power management integrated circuit (PMIC) configured to supply power to the first package and the second package; a core member having a through-hole in which the PMIC is disposed; a first redistribution layer on the core member, and electrically connected to the first package; a second redistribution layer under the core member, and electrically connected to the second package; core vias penetrating the core member, and electrically connecting the first redistribution layer with the second redistribution layer; and a first signal path electrically connecting the first package with the second package.

    PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE SAME
    4.
    发明申请
    PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权
    包装衬底和具有该衬底的半导体封装

    公开(公告)号：US20140140026A1

    公开(公告)日：2014-05-22

    申请号：US14147114

    申请日：2014-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Se-Ho YOU ,  Heeseok LEE ,  Chiyoung LEE ,  Yun-Hee LEE

    IPC: H05K1/18

    CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/48227 ,  H01L2225/107 ,  H01L2924/1515 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/18 ,  H05K1/181 ,  Y02P70/611

    Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

    Abstract translation: 提供了封装基板和半导体封装。 封装基板包括具有上表面和与上表面相对的下表面的主体，附接到下表面的多个外部端子，以及形成在下表面的多个外部区域中的多个凹槽 端子未连接。 半导体封装包括封装衬底，安装在半导体衬底的上表面上的半导体芯片，以及提供安装有封装衬底的区域的板，并且安装有与多个沟槽垂直对准的多个安装元件 并插入到多个槽中。

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明公开
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230335501A1

    公开(公告)日：2023-10-19

    申请号：US18214172

    申请日：2023-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghwa KIM ,  Heeseok LEE

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

    CPC classification number: H01L23/5384 ,  H01L25/0657 ,  H01L23/5386 ,  H01L23/5385 ,  H01L23/31

    Abstract: A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210272906A1

    公开(公告)日：2021-09-02

    申请号：US17039983

    申请日：2020-09-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghwa KIM ,  Heeseok LEE

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31

    Abstract: A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.

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