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    PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE SAME
    4.
    发明申请
    PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE HAVING THE SAME 有权
    包装衬底和具有该衬底的半导体封装

    公开(公告)号：US20140140026A1

    公开(公告)日：2014-05-22

    申请号：US14147114

    申请日：2014-01-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Se-Ho YOU ,  Heeseok LEE ,  Chiyoung LEE ,  Yun-Hee LEE

    IPC: H05K1/18

    CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/48227 ,  H01L2225/107 ,  H01L2924/1515 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/18 ,  H05K1/181 ,  Y02P70/611

    Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

    Abstract translation: 提供了封装基板和半导体封装。 封装基板包括具有上表面和与上表面相对的下表面的主体，附接到下表面的多个外部端子，以及形成在下表面的多个外部区域中的多个凹槽 端子未连接。 半导体封装包括封装衬底，安装在半导体衬底的上表面上的半导体芯片，以及提供安装有封装衬底的区域的板，并且安装有与多个沟槽垂直对准的多个安装元件 并插入到多个槽中。

    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
    5.
    发明公开
    SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240213166A1

    公开(公告)日：2024-06-27

    申请号：US18377569

    申请日：2023-10-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Se-Ho YOU ,  Byeong Uk JEON

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

    CPC classification number: H01L23/5381 ,  H01L23/3185 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/16258 ,  H01L2224/17153

    Abstract: A semiconductor package including a package substrate, a bridge structure stacked on the package substrate, a first molding member surrounding a side surface of the bridge structure, a trace pattern extending along an upper surface of the bridge structure and an upper surface of the first molding member, a via pattern penetrating through the first molding member and electrically connecting the package substrate and the trace pattern to each other, and a first semiconductor chip and a second semiconductor chip each stacked on the upper surface of the first molding member and electrically connected to each other by the bridge structure. The first semiconductor chip and the second semiconductor chip are arranged along a first direction parallel to an upper surface of the package substrate and the trace pattern extends in the first direction and is electrically connected to at least one of the first semiconductor chip and the second semiconductor chip.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230133977A1

    公开(公告)日：2023-05-04

    申请号：US17837379

    申请日：2022-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Se-Ho YOU ,  Ju-Il CHOI

    IPC: H01L27/108

    Abstract: A semiconductor device including a substrate and first and second packages thereon, the first package includes a first lower redistribution layer; a first core semiconductor stack thereon and including a first core chip and a first through via stacked on the first lower redistribution layer; and a first memory semiconductor stack on the first lower redistribution layer and including first memory chips stacked on the first lower redistribution layer, the second package includes a second lower redistribution layer; a second core semiconductor stack thereon and including a second core chip on the second lower redistribution layer; and a second memory semiconductor stack on the second lower redistribution layer and including second memory chips stacked on the second lower redistribution layer, the first through via penetrates the first core semiconductor stack, and the first and second lower redistribution layers are electrically connected to each other through the first through via.

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