公开(公告)号：US10303372B2

公开(公告)日：2019-05-28

申请号：US15366137

申请日：2016-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Cho ,  Sungyong Seo ,  Sun-Young Lim ,  Uksong Kang ,  Chankyung Kim ,  Duckhyun Chang ,  JinHyeok Choi

IPC: G06F13/16 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G06F12/0868 ,  G06F12/0893 ,  G11C11/00

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US20190278487A1

公开(公告)日：2019-09-12

申请号：US16414893

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin CHO ,  Sungyong Seo ,  Sun-Young Lim ,  Uksong Kang ,  Chankyung Kim ,  Duckhyun Chang ,  JinHyeok Choi

IPC: G06F3/06 ,  G06F12/0893 ,  G11C11/00 ,  G06F13/16 ,  G06F12/0868 ,  G11C16/26 ,  G11C16/10

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US11614866B2

公开(公告)日：2023-03-28

申请号：US17389834

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Cho ,  Sungyong Seo ,  Sun-Young Lim ,  Uksong Kang ,  Chankyung Kim ,  Duckhyun Chang ,  JinHyeok Choi

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G06F12/0868 ,  G06F12/0893 ,  G11C11/00 ,  G06F13/16 ,  G06F12/121

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

公开(公告)号：US11106363B2

公开(公告)日：2021-08-31

申请号：US16414893

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Cho ,  Sungyong Seo ,  Sun-Young Lim ,  Uksong Kang ,  Chankyung Kim ,  Duckhyun Chang ,  JinHyeok Choi

IPC: G06F12/121 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G06F12/0868 ,  G06F12/0893 ,  G11C11/00 ,  G06F13/16

Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.