公开(公告)号：US20250017021A1

公开(公告)日：2025-01-09

申请号：US18630647

申请日：2024-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seulji SONG ,  Suhyun BANG ,  Hwayeong LEE

IPC: H10B53/30 ,  H10B53/20

Abstract: An integrated circuit device including first and second vertical transistors, wherein the first and second vertical transistors are apart from each other in a first direction; a common plate between the first and second vertical transistors; a first capacitor structure between the first vertical transistor and the common plate including a first lower electrode extending in the first direction, a first dielectric layer on the first lower electrode, and a first upper electrode on the first dielectric layer; and a second capacitor structure between the second vertical transistor and the common plate including a second lower electrode extending in the first direction, a second dielectric layer on the second lower electrode, and a second upper electrode on the second dielectric layer, wherein the first upper electrode is on a lower surface of the common plate, and the second upper electrode is on an upper surface of the common plate.

公开(公告)号：US20240237348A1

公开(公告)日：2024-07-11

申请号：US18403115

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwayeong LEE ,  Hunmo Yang ,  Seulji Song

IPC: H10B43/27 ,  G11C5/06 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  G11C5/063 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor memory device includes a semiconductor substrate; a plurality of word line layers on the semiconductor substrate, each word line layer of the plurality of word line layers including an insulating line and a word line; a plurality of insulating layers in spaces between the plurality of word line layers, the plurality of insulating layers being apart from each other in a vertical direction on the semiconductor substrate; a channel structure extending in the vertical direction on the semiconductor substrate, the channel structure including a channel region and a gate dielectric layer surrounding the channel region; and a bit line on the channel structure, the bit line extending in a first horizontal direction perpendicular to the vertical direction and being connected to the channel structure, wherein the word line of each word line layer of the plurality of word line layers has a meandering shape.