公开(公告)号：US20230320074A1

公开(公告)日：2023-10-05

申请号：US17948796

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jongmin KIM ,  Chansic YOON ,  Hyosub KIM ,  Sohyun PARK ,  Junhyeok AHN

IPC: H01L27/108 ,  H01L29/417

CPC classification number: H01L27/10814 ,  H01L29/41725

Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

公开(公告)号：US20240188285A1

公开(公告)日：2024-06-06

申请号：US18509539

申请日：2023-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjun KIM ,  Hyosub KIM ,  Junhyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315

Abstract: The semiconductor device includes an active pattern; a gate structure in an upper portion of the active pattern; a bit line structure on the active pattern, the bit line structure including a first metal; a first spacer on a sidewall of the bit line structure, the first spacer including an oxide of a second metal that has an ionization energy smaller than that of the first metal; a second spacer on an outer sidewall of the first spacer, the second spacer including an oxide of a third metal; a third spacer on a lower portion of an outer sidewall of the second spacer, the third spacer including a nitride; a fourth spacer on an upper portion of the outer sidewall of the second spacer and the third spacer; a fifth spacer and a sixth spacer sequentially stacked in a horizontal direction from an outer sidewall of the fourth spacer.

公开(公告)号：US20230247822A1

公开(公告)日：2023-08-03

申请号：US18072885

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Junhyeok AHN ,  Hyosub KIM ,  Sohyun PARK

IPC: H10B12/00

CPC classification number: H01L27/10805

Abstract: A semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A first silicide layer is disposed on both sidewalls of the first contact layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and is in direct contact with the second silicide layer.

公开(公告)号：US20230137846A1

公开(公告)日：2023-05-04

申请号：US17969966

申请日：2022-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok AHN ,  Sohyun PARK ,  Hyosub KIM

IPC: H01L27/108

Abstract: Provided is a semiconductor device including a substrate including a cell array area and a peripheral circuit area and including a plurality of first active areas defined in the cell array area and at least one second active area defined in the peripheral circuit area; a plurality of bit lines arranged in the cell array area of the substrate and extending in a first direction; a plurality of cell pad structures arranged between the bit lines and each including a first conductive layer, a first intermediate layer, and a first metal layer that are sequentially arranged on a top surface of the first active area; and a peripheral circuit gate electrode disposed on the peripheral circuit area of the substrate and including a second conductive layer, a second intermediate layer, and a second metal layer sequentially arranged on the at least one second active area.